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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-06-27 15:39:19 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-06-27 15:39:19 +0000 |
| commit | a3134fae172e32e39adde797070868f5faf745eb (patch) | |
| tree | 865830ad0b7497d965287875ab3d73b855f8934a /llvm/test/MC/Disassembler/Mips/mips64r6 | |
| parent | 8c7e29d583eb54b2dd3e4c105e63ce3b4299433b (diff) | |
| download | bcm5719-llvm-a3134fae172e32e39adde797070868f5faf745eb.tar.gz bcm5719-llvm-a3134fae172e32e39adde797070868f5faf745eb.zip | |
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.
Summary:
Previously it (incorrectly) used GPR's.
Patch by Simon Dardis. A couple small corrections by myself.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10567
llvm-svn: 240883
Diffstat (limited to 'llvm/test/MC/Disassembler/Mips/mips64r6')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index 4afd9cc5c4f..157e33593e3 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -92,8 +92,10 @@ 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3 +0x00 0x50 0x38 0x40 # CHECK: dmfc0 $24, $10, 0 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4 +0x00 0x50 0xa4 0x40 # CHECK: dmtc0 $4, $10, 0 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4 @@ -119,12 +121,14 @@ 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4 +0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4 +0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index c41ba990122..91051333880 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -92,8 +92,10 @@ 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3 +0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 +0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4 0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4 0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4 @@ -121,6 +123,7 @@ 0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 @@ -129,6 +132,7 @@ 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 |
