diff options
| author | Colin LeMahieu <colinl@codeaurora.org> | 2015-01-05 20:56:41 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2015-01-05 20:56:41 +0000 |
| commit | 28bb02a8c7ac87c9de1b66938f268d66cdd1e67a (patch) | |
| tree | 6a4fdbd84ba7dc90153232643c9079c74f77648c /llvm/test/MC/Disassembler/Hexagon | |
| parent | 1c00c9f7fc9265f8c9e5c92d92ac403c6ef1c437 (diff) | |
| download | bcm5719-llvm-28bb02a8c7ac87c9de1b66938f268d66cdd1e67a.tar.gz bcm5719-llvm-28bb02a8c7ac87c9de1b66938f268d66cdd1e67a.zip | |
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
llvm-svn: 225201
Diffstat (limited to 'llvm/test/MC/Disassembler/Hexagon')
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt | 10 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt | 16 |
3 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt index 7d25fdbcf2c..b86165e496e 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -122,6 +122,12 @@ # CHECK: r17 = round(r21, #31) 0xd1 0xdf 0xf5 0x8c # CHECK: r17 = round(r21, #31):sat +0x11 0xdf 0xd5 0xc6 +# CHECK: r17 = cround(r21, r31) +0x91 0xdf 0xd5 0xc6 +# CHECK: r17 = round(r21, r31) +0xd1 0xdf 0xd5 0xc6 +# CHECK: r17 = round(r21, r31):sat 0x71 0xd5 0x1f 0xef # CHECK: r17 += sub(r21, r31) 0x11 0xd5 0x3f 0xd5 diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt index f69e409e77d..b6ccaa6f31e 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt @@ -1,5 +1,15 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0xb1 0xdf 0x35 0xd7 +# CHECK: r17 = add(#21, mpyi(r21, r31)) +0xbf 0xd1 0x35 0xd8 +# CHECK: r17 = add(#21, mpyi(r21, #31)) +0xb5 0xd1 0x3f 0xdf +# CHECK: r17 = add(r21, mpyi(#84, r31)) +0xf5 0xf1 0xb5 0xdf +# CHECK: r17 = add(r21, mpyi(r21, #31)) +0x15 0xd1 0x1f 0xe3 +# CHECK: r17 = add(r21, mpyi(r17, r31)) 0xf1 0xc3 0x15 0xe0 # CHECK: r17 =+ mpyi(r21, #31) 0xf1 0xc3 0x95 0xe0 diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt index f18407a4b64..5e26c1b669b 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt @@ -36,6 +36,14 @@ # CHECK: r17 += lsr(r21, #31) 0xd1 0xdf 0x15 0x8e # CHECK: r17 += asl(r21, #31) +0x4c 0xf7 0x11 0xde +# CHECK: r17 = add(#21, asl(r17, #23)) +0x4e 0xf7 0x11 0xde +# CHECK: r17 = sub(#21, asl(r17, #23)) +0x5c 0xf7 0x11 0xde +# CHECK: r17 = add(#21, lsr(r17, #23)) +0x5e 0xf7 0x11 0xde +# CHECK: r17 = sub(#21, lsr(r17, #23)) 0xf1 0xd5 0x1f 0xc4 # CHECK: r17 = addasl(r21, r31, #7) 0x10 0xdf 0x54 0x82 @@ -54,6 +62,14 @@ # CHECK: r17:16 ^= lsr(r21:20, #31) 0x50 0xdf 0x94 0x82 # CHECK: r17:16 ^= asl(r21:20, #31) +0x48 0xff 0x11 0xde +# CHECK: r17 = and(#21, asl(r17, #31)) +0x4a 0xff 0x11 0xde +# CHECK: r17 = or(#21, asl(r17, #31)) +0x58 0xff 0x11 0xde +# CHECK: r17 = and(#21, lsr(r17, #31)) +0x5a 0xff 0x11 0xde +# CHECK: r17 = or(#21, lsr(r17, #31)) 0x11 0xdf 0x55 0x8e # CHECK: r17 &= asr(r21, #31) 0x31 0xdf 0x55 0x8e |
