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| author | Quentin Colombet <qcolombet@apple.com> | 2013-04-12 18:47:25 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2013-04-12 18:47:25 +0000 |
| commit | c313220b1884dbe600cee2103c3af4315914caf5 (patch) | |
| tree | f3f98b0c458547b109b7fc3f6ed96be4e7b245df /llvm/test/MC/Disassembler/ARM | |
| parent | 1eb3b89d9278ae4e049f5cd9a436a595d6c7e131 (diff) | |
| download | bcm5719-llvm-c313220b1884dbe600cee2103c3af4315914caf5.tar.gz bcm5719-llvm-c313220b1884dbe600cee2103c3af4315914caf5.zip | |
ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
llvm-svn: 179398
Diffstat (limited to 'llvm/test/MC/Disassembler/ARM')
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/arm-tests.txt | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 0c9aaab38c7..98daaa7649a 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -51,24 +51,48 @@ # CHECKx: ldclvc p5, cr15, [r8], #-0 #0x00 0xf5 0x78 0x7c +# CHECK: ldc p13, c9, [r2, #0]! +0x00 0x9d 0xb2 0xed + +# CHECK: ldcl p1, c9, [r3, #0]! +0x00 0x91 0xf3 0xed + # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 # CHECK: ldr r5, [r7, -r10, lsl #2] 0x0a 0x51 0x17 0xe7 +# CHECK: ldr r4, [r5, #0]! +0x00 0x40 0xb5 0xe5 + +# CHECK: ldrb lr, [r10, #0]! +0x00 0xe0 0xfa 0xe5 + +# CHECK: ldrd r4, r5, [r0, #0]! +0xd0 0x40 0xe0 0xe1 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 # CHECK: ldrh r0, [r2] 0xb0 0x00 0xd2 0xe1 +# CHECK: ldrh lr, [sp, #0]! +0xb0 0xe0 0xfd 0xe1 + # CHECK: ldrht r0, [r2], #15 0xbf 0x00 0xf2 0xe0 +# CHECK: ldrsb r1, [lr, #0]! +0xd0 0x10 0xfe 0xe1 + # CHECK: ldrsbtvs lr, [r2], -r9 0xd9 0xe0 0x32 0x60 +# CHECK: ldrsh r9, [r1, #0] +0xf0 0x90 0xf1 0xe1 + # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 @@ -245,9 +269,27 @@ # CHECK: stc p2, c4, [r9], {157} 0x9d 0x42 0x89 0xec +# CHECK: stc p15, c0, [r3, #0]! +0x00 0x0f 0xa3 0xed + # CHECK: stc2 p2, c4, [r9], {157} 0x9d 0x42 0x89 0xfc +# CHECK: stcl p13, c12, [r9, #0]! +0x00 0xcd 0xe9 0xed + +# CHECK: str pc, [r11, #0]! +0x00 0xf0 0xab 0xe5 + +# CHECK: strb r9, [r10, #0]! +0x00 0x90 0xea 0xe5 + +# CHECK: strd r12, sp, [r6, #0]! +0xf0 0xc0 0xe6 0xe1 + +# CHECK: strh r7, [r9, #0]! +0xb0 0x70 0xe9 0xe1 + # CHECK: bne #-24 0xfa 0xff 0xff 0x1a |
