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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-06-03 14:03:27 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-06-03 14:03:27 +0000 |
| commit | d906bf13699ca115a27d78e2d42ab71c2e851fe1 (patch) | |
| tree | 4fda9bf6899ecf2156a6a57cfcbbc13452736025 /llvm/test/MC/Disassembler/AArch64 | |
| parent | 60adb9229c2f5daad51625a4e03497b293253e5b (diff) | |
| download | bcm5719-llvm-d906bf13699ca115a27d78e2d42ab71c2e851fe1.tar.gz bcm5719-llvm-d906bf13699ca115a27d78e2d42ab71c2e851fe1.zip | |
RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
new instruction to ARM and AArch64 targets and several system registers.
Patch by: Roger Ferrer Ibanez and Oliver Stannard
Differential Revision: http://reviews.llvm.org/D20282
llvm-svn: 271670
Diffstat (limited to 'llvm/test/MC/Disassembler/AArch64')
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/ras-extension.txt | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/AArch64/ras-extension.txt b/llvm/test/MC/Disassembler/AArch64/ras-extension.txt new file mode 100644 index 00000000000..241dc558d08 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/ras-extension.txt @@ -0,0 +1,47 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+ras --disassemble < %s | FileCheck %s + +[0x1f,0x22,0x03,0xd5] +# CHECK: esb + +# CHECK: msr ERRSELR_EL1, x0 +# CHECK: msr ERXCTLR_EL1, x0 +# CHECK: msr ERXSTATUS_EL1, x0 +# CHECK: msr ERXADDR_EL1, x0 +# CHECK: msr ERXMISC0_EL1, x0 +# CHECK: msr ERXMISC1_EL1, x0 +# CHECK: msr DISR_EL1, x0 +# CHECK: msr VDISR_EL2, x0 +# CHECK: msr VSESR_EL2, x0 +[0x20,0x53,0x18,0xd5] +[0x20,0x54,0x18,0xd5] +[0x40,0x54,0x18,0xd5] +[0x60,0x54,0x18,0xd5] +[0x00,0x55,0x18,0xd5] +[0x20,0x55,0x18,0xd5] +[0x20,0xc1,0x18,0xd5] +[0x20,0xc1,0x1c,0xd5] +[0x60,0x52,0x1c,0xd5] + +# CHECK: mrs x0, ERRSELR_EL1 +# CHECK: mrs x0, ERXCTLR_EL1 +# CHECK: mrs x0, ERXSTATUS_EL1 +# CHECK: mrs x0, ERXADDR_EL1 +# CHECK: mrs x0, ERXMISC0_EL1 +# CHECK: mrs x0, ERXMISC1_EL1 +# CHECK: mrs x0, DISR_EL1 +# CHECK: mrs x0, VDISR_EL2 +# CHECK: mrs x0, VSESR_EL2 +[0x20,0x53,0x38,0xd5] +[0x20,0x54,0x38,0xd5] +[0x40,0x54,0x38,0xd5] +[0x60,0x54,0x38,0xd5] +[0x00,0x55,0x38,0xd5] +[0x20,0x55,0x38,0xd5] +[0x20,0xc1,0x38,0xd5] +[0x20,0xc1,0x3c,0xd5] +[0x60,0x52,0x3c,0xd5] + +# CHECK: mrs x0, ERRIDR_EL1 +# CHECK: mrs x0, ERXFR_EL1 +[0x00,0x53,0x38,0xd5] +[0x00,0x54,0x38,0xd5] |
