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| author | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-14 01:57:32 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-14 01:57:32 +0000 |
| commit | bb60ccf3558c6dc929438eb1a4877f468e476efd (patch) | |
| tree | c481e2573d9a388754208fb679fccd4bf451a28f /llvm/test/MC/Disassembler/AArch64 | |
| parent | f6171b3cdf2137979979935a16521869b5b498f5 (diff) | |
| download | bcm5719-llvm-bb60ccf3558c6dc929438eb1a4877f468e476efd.tar.gz bcm5719-llvm-bb60ccf3558c6dc929438eb1a4877f468e476efd.zip | |
Implement AArch64 NEON instruction set AdvSIMD (table).
llvm-svn: 194648
Diffstat (limited to 'llvm/test/MC/Disassembler/AArch64')
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/neon-instructions.txt | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/llvm/test/MC/Disassembler/AArch64/neon-instructions.txt b/llvm/test/MC/Disassembler/AArch64/neon-instructions.txt index b9ea7c140be..c1659019a87 100644 --- a/llvm/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,4 @@ -G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -2387,3 +2387,42 @@ G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | 0x51 0x04 0x14 0x5e 0x86 0x05 0x18 0x5e +#---------------------------------------------------------------------- +# Table look up +#---------------------------------------------------------------------- +0x20,0x00,0x02,0x0e +0xf0,0x23,0x02,0x0e +0x20,0x40,0x02,0x0e +0xf0,0x62,0x02,0x0e +# CHECK: tbl v0.8b, {v1.16b}, v2.8b +# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b +# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b + +0x20,0x00,0x02,0x4e +0xf0,0x23,0x02,0x4e +0x20,0x40,0x02,0x4e +0xe0,0x63,0x02,0x4e +# CHECK: tbl v0.16b, {v1.16b}, v2.16b +# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b +# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b + +0x20,0x10,0x02,0x0e +0xf0,0x33,0x02,0x0e +0x20,0x50,0x02,0x0e +0xf0,0x72,0x02,0x0e +# CHECK: tbx v0.8b, {v1.16b}, v2.8b +# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b +# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b + +0x20,0x10,0x02,0x4e +0xf0,0x33,0x02,0x4e +0x20,0x50,0x02,0x4e +0xf0,0x73,0x02,0x4e +# CHECK: tbx v0.16b, {v1.16b}, v2.16b +# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b +# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b + |
