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| author | Petr Pavlu <petr.pavlu@arm.com> | 2015-07-15 08:10:30 +0000 |
|---|---|---|
| committer | Petr Pavlu <petr.pavlu@arm.com> | 2015-07-15 08:10:30 +0000 |
| commit | 097adfb98cb61314bd98be2226ad6120cca92a87 (patch) | |
| tree | 725f371d99407e54181cb4bb0d644f91a8a4680e /llvm/test/MC/Disassembler/AArch64 | |
| parent | a033bbbe962be82a4b95413c153f71edc9b23760 (diff) | |
| download | bcm5719-llvm-097adfb98cb61314bd98be2226ad6120cca92a87.tar.gz bcm5719-llvm-097adfb98cb61314bd98be2226ad6120cca92a87.zip | |
[AArch64] Fix problems in decoding generic MSR instructions
Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.
Differential Revision: http://reviews.llvm.org/D7174
llvm-svn: 242276
Diffstat (limited to 'llvm/test/MC/Disassembler/AArch64')
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 615d9ba19ca..089fc821097 100644 --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -4172,12 +4172,16 @@ # CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} # CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} +# CHECK: mrs xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}} # CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 # CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 +# CHECK: msr {{s0_0_c4_c0_0|S0_0_C4_C0_0}}, xzr 0xac 0xf1 0x3f 0xd5 0xed 0xbf 0x3a 0xd5 +0x1f 0x40 0x20 0xd5 0x0c 0xf0 0x18 0xd5 0xe5 0xbd 0x1f 0xd5 +0x1f 0x40 0x00 0xd5 #------------------------------------------------------------------------------ # Test and branch (immediate) |
