ARM: implement support for the UDF mnemonic

The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

llvm-svn: 208751

6 files changed, 98 insertions, 0 deletions

diff --git a/llvm/test/MC/ARM/udf-arm-diagnostics.s b/llvm/test/MC/ARM/udf-arm-diagnostics.s
new file mode 100644
index 00000000000..9ec9bf2124f
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-arm-diagnostics.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s
+
+	.syntax unified
+	.text
+	.arm
+
+undefined:
+	udfpl
+
+@ CHECK: error: instruction 'udf' is not predicable, but condition code specified
+@ CHECK: 	udfpl
+@ CHECK: 	^
+
+	udf #65536
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: 	udf #65536
+@ CHECK: 	    ^
+
diff --git a/llvm/test/MC/ARM/udf-arm.s b/llvm/test/MC/ARM/udf-arm.s
new file mode 100644
index 00000000000..a9d19ca66e6
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-arm.s
@@ -0,0 +1,11 @@
+@ RUN: llvm-mc -triple arm-eabi -show-encoding %s | FileCheck %s
+
+	.syntax unified
+	.text
+	.arm
+
+undefined:
+	udf #0
+
+@ CHECK: udf	#0                      @ encoding: [0xf0,0x00,0xf0,0xe7]
+
diff --git a/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s
new file mode 100644
index 00000000000..f8375601a03
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s
@@ -0,0 +1,25 @@
+@ RUN: not llvm-mc -triple thumbv7-eabi -mattr +thumb2 %s 2>&1 | FileCheck %s
+
+	.syntax unified
+	.text
+	.thumb
+
+undefined:
+	udfpl
+
+@ CHECK: error: instruction 'udf' is not predicable, but condition code specified
+@ CHECK: 	udfpl
+@ CHECK: 	^
+
+	udf #256
+
+@ CHECK: error: instruction requires: arm-mode
+@ CHECK: 	udf #256
+@ CHECK: 	^
+
+	udf.w #65536
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: 	udf.w #65536
+@ CHECK: 	      ^
+
diff --git a/llvm/test/MC/ARM/udf-thumb-2.s b/llvm/test/MC/ARM/udf-thumb-2.s
new file mode 100644
index 00000000000..beb6549cb08
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-2.s
@@ -0,0 +1,13 @@
+@ RUN: llvm-mc -triple thumbv7-eabi -mattr +thumb2 -show-encoding %s | FileCheck %s
+
+	.syntax unified
+	.text
+	.thumb
+
+undefined:
+	udf #0
+	udf.w #0
+
+@ CHECK: udf	#0                      @ encoding: [0x00,0xde]
+@ CHECK: udf.w	#0                      @ encoding: [0xf0,0xf7,0x00,0xa0]
+
diff --git a/llvm/test/MC/ARM/udf-thumb-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-diagnostics.s
new file mode 100644
index 00000000000..51388d0f10d
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-diagnostics.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple thumbv6m-eabi %s 2>&1 | FileCheck %s
+
+	.syntax unified
+	.text
+	.thumb
+
+undefined:
+	udfpl
+
+@ CHECK: error: conditional execution not supported in Thumb1
+@ CHECK: 	udfpl
+@ CHECK: 	^
+
+	udf #256
+
+@ CHECK: error: instruction requires: arm-mode
+@ CHECK: 	udf #256
+@ CHECK: 	^
+
diff --git a/llvm/test/MC/ARM/udf-thumb.s b/llvm/test/MC/ARM/udf-thumb.s
new file mode 100644
index 00000000000..10b3aff1aa3
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb.s
@@ -0,0 +1,11 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -show-encoding %s | FileCheck %s
+
+	.syntax unified
+	.text
+	.thumb
+
+undefined:
+	udf #0
+
+@ CHECK: udf	#0                      @ encoding: [0x00,0xde]
+