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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-10-11 14:53:26 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-10-11 14:53:26 +0000 |
| commit | c4995076c6bd3706918930de436246ec4257c364 (patch) | |
| tree | f6b25c721c9ee596eec81f5731675531c3e97219 /llvm/test/MC/AMDGPU | |
| parent | b67d3df1c11e8c27fd33bed308fe326242f9be43 (diff) | |
| download | bcm5719-llvm-c4995076c6bd3706918930de436246ec4257c364.tar.gz bcm5719-llvm-c4995076c6bd3706918930de436246ec4257c364.zip | |
[AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
See https://bugs.llvm.org/show_bug.cgi?id=37941
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D68787
llvm-svn: 374561
Diffstat (limited to 'llvm/test/MC/AMDGPU')
| -rw-r--r-- | llvm/test/MC/AMDGPU/ds-gfx9.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/gfx10_asm_all.s | 56 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/gfx10_asm_err.s | 4 |
3 files changed, 34 insertions, 34 deletions
diff --git a/llvm/test/MC/AMDGPU/ds-gfx9.s b/llvm/test/MC/AMDGPU/ds-gfx9.s index 7c67a3f7edd..810ccb018e8 100644 --- a/llvm/test/MC/AMDGPU/ds-gfx9.s +++ b/llvm/test/MC/AMDGPU/ds-gfx9.s @@ -33,10 +33,10 @@ ds_write_b16_d16_hi v8, v2 // VI-ERR: error: instruction not supported on this GPU // GFX9: ds_write_b16_d16_hi v8, v2 ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00] -ds_write_addtid_b32 v8, v2 +ds_write_addtid_b32 v8 // VI-ERR: error: instruction not supported on this GPU -// GFX9: ds_write_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x3a,0xd8,0x08,0x02,0x00,0x00] +// GFX9: ds_write_addtid_b32 v8 ; encoding: [0x00,0x00,0x3a,0xd8,0x00,0x08,0x00,0x00] -ds_read_addtid_b32 v8, v2 +ds_read_addtid_b32 v8 // VI-ERR: error: instruction not supported on this GPU -// GFX9: ds_read_addtid_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd9,0x02,0x00,0x00,0x08] +// GFX9: ds_read_addtid_b32 v8 ; encoding: [0x00,0x00,0x6c,0xd9,0x00,0x00,0x00,0x08] diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_all.s b/llvm/test/MC/AMDGPU/gfx10_asm_all.s index 4916702dbcb..c358482eaa3 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_all.s @@ -6538,47 +6538,47 @@ ds_read_u16_d16_hi v5, v1 offset:4 ds_read_u16_d16_hi v5, v1 offset:65535 gds // GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05] -ds_write_addtid_b32 v5, v1 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0x01,0x00,0x00] +ds_write_addtid_b32 v5 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00] -ds_write_addtid_b32 v255, v1 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc0,0xda,0xff,0x01,0x00,0x00] +ds_write_addtid_b32 v255 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00] -ds_write_addtid_b32 v5, v255 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x05,0xff,0x00,0x00] +ds_write_addtid_b32 v5 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00] -ds_write_addtid_b32 v5, v1 -// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] +ds_write_addtid_b32 v5 +// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00] -ds_write_addtid_b32 v5, v1 offset:0 -// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] +ds_write_addtid_b32 v5 offset:0 +// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00] -ds_write_addtid_b32 v5, v1 offset:4 -// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x05,0x01,0x00,0x00] +ds_write_addtid_b32 v5 offset:4 +// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00] -ds_write_addtid_b32 v5, v1 offset:65535 gds -// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x05,0x01,0x00,0x00] +ds_write_addtid_b32 v5 offset:65535 gds +// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00] -ds_read_addtid_b32 v5, v1 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0x05] +ds_read_addtid_b32 v5 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05] -ds_read_addtid_b32 v255, v1 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x01,0x00,0x00,0xff] +ds_read_addtid_b32 v255 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff] -ds_read_addtid_b32 v5, v255 offset:65535 -// GFX10: encoding: [0xff,0xff,0xc4,0xda,0xff,0x00,0x00,0x05] +ds_read_addtid_b32 v5 offset:65535 +// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05] -ds_read_addtid_b32 v5, v1 -// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] +ds_read_addtid_b32 v5 +// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05] -ds_read_addtid_b32 v5, v1 offset:0 -// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] +ds_read_addtid_b32 v5 offset:0 +// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05] -ds_read_addtid_b32 v5, v1 offset:4 -// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x01,0x00,0x00,0x05] +ds_read_addtid_b32 v5 offset:4 +// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05] -ds_read_addtid_b32 v5, v1 offset:65535 gds -// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x01,0x00,0x00,0x05] +ds_read_addtid_b32 v5 offset:65535 gds +// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05] ds_permute_b32 v0, v1, v2 // GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_err.s index 4203fd51566..eff0cff4272 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_err.s @@ -35,10 +35,10 @@ ds_read_u16_d16 v5, v1 ds_read_u16_d16_hi v5, v1 // GFX6-8: error: instruction not supported on this GPU -ds_write_addtid_b32 v5, v1 +ds_write_addtid_b32 v5 // GFX6-8: error: instruction not supported on this GPU -ds_read_addtid_b32 v5, v1 +ds_read_addtid_b32 v5 // GFX6-8: error: instruction not supported on this GPU // GFX8+. |
