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| author | Michael Berg <michael_c_berg@apple.com> | 2019-07-10 18:23:26 +0000 |
|---|---|---|
| committer | Michael Berg <michael_c_berg@apple.com> | 2019-07-10 18:23:26 +0000 |
| commit | f4572249d78d13b16cb287500a3bcd226ececb31 (patch) | |
| tree | 7d0ac9329606f586b942e959544f058c6db52fe1 /llvm/test/CodeGen | |
| parent | 6d1a64e489ecd71d042609d4f79901dba3cb060b (diff) | |
| download | bcm5719-llvm-f4572249d78d13b16cb287500a3bcd226ececb31.tar.gz bcm5719-llvm-f4572249d78d13b16cb287500a3bcd226ececb31.zip | |
Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang. I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it. Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context.
Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm
Reviewed By: arsenm
Subscribers: michele.scandale, wdng, javed.absar
Differential Revision: https://reviews.llvm.org/D64450
llvm-svn: 365679
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/nnan-fsub.ll (renamed from llvm/test/CodeGen/ARM/unsafe-fsub.ll) | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/fmul-combines.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/fp-fast.ll | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/ARM/unsafe-fsub.ll b/llvm/test/CodeGen/ARM/nnan-fsub.ll index 0c5702aa5fa..01839083547 100644 --- a/llvm/test/CodeGen/ARM/unsafe-fsub.ll +++ b/llvm/test/CodeGen/ARM/nnan-fsub.ll @@ -1,5 +1,5 @@ ; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s -; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s +; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s target triple = "armv7-apple-ios" diff --git a/llvm/test/CodeGen/X86/fmul-combines.ll b/llvm/test/CodeGen/X86/fmul-combines.ll index f9843dced1b..3a2b7bc4a82 100644 --- a/llvm/test/CodeGen/X86/fmul-combines.ll +++ b/llvm/test/CodeGen/X86/fmul-combines.ll @@ -76,12 +76,12 @@ define <4 x float> @constant_fold_fmul_v4f32_undef(<4 x float> %x) { ret <4 x float> %y } -define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 { -; CHECK-LABEL: fmul0_v4f32: +define <4 x float> @fmul0_v4f32_nsz_nnan(<4 x float> %x) #0 { +; CHECK-LABEL: fmul0_v4f32_nsz_nnan: ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0> + %y = fmul nnan nsz <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0> ret <4 x float> %y } @@ -90,7 +90,7 @@ define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, <float undef, float 0.0, float undef, float 0.0> + %y = fmul nnan nsz <4 x float> %x, <float undef, float 0.0, float undef, float 0.0> ret <4 x float> %y } diff --git a/llvm/test/CodeGen/X86/fp-fast.ll b/llvm/test/CodeGen/X86/fp-fast.ll index 7abedfd2d17..81dd983d94c 100644 --- a/llvm/test/CodeGen/X86/fp-fast.ll +++ b/llvm/test/CodeGen/X86/fp-fast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math --enable-no-nans-fp-math < %s | FileCheck %s define float @test1(float %a) { ; CHECK-LABEL: test1: |
