diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/nnan-fsub.ll (renamed from llvm/test/CodeGen/ARM/unsafe-fsub.ll) | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/fmul-combines.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/fp-fast.ll | 2 |
4 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 232bfe46dc3..320db83566b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12030,8 +12030,8 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { // Selection pass has a hard time dealing with FP constants. bool AllowNewConst = (Level < AfterLegalizeDAG); - // If 'unsafe math' or nnan is enabled, fold lots of things. - if ((Options.UnsafeFPMath || Flags.hasNoNaNs()) && AllowNewConst) { + // If nnan is enabled, fold lots of things. + if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) { // If allowed, fold (fadd (fneg x), x) -> 0.0 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) return DAG.getConstantFP(0.0, DL, VT); @@ -12171,7 +12171,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { if (N0 == N1) { // (fsub x, x) -> 0.0 - if (Options.UnsafeFPMath || Flags.hasNoNaNs()) + if (Options.NoNaNsFPMath || Flags.hasNoNaNs()) return DAG.getConstantFP(0.0f, DL, VT); } @@ -12249,7 +12249,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) { if (SDValue NewSel = foldBinOpIntoSelect(N)) return NewSel; - if (Options.UnsafeFPMath || + if ((Options.NoNaNsFPMath && Options.NoSignedZerosFPMath) || (Flags.hasNoNaNs() && Flags.hasNoSignedZeros())) { // fold (fmul A, 0) -> 0 if (N1CFP && N1CFP->isZero()) diff --git a/llvm/test/CodeGen/ARM/unsafe-fsub.ll b/llvm/test/CodeGen/ARM/nnan-fsub.ll index 0c5702aa5fa..01839083547 100644 --- a/llvm/test/CodeGen/ARM/unsafe-fsub.ll +++ b/llvm/test/CodeGen/ARM/nnan-fsub.ll @@ -1,5 +1,5 @@ ; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s -; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s +; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s target triple = "armv7-apple-ios" diff --git a/llvm/test/CodeGen/X86/fmul-combines.ll b/llvm/test/CodeGen/X86/fmul-combines.ll index f9843dced1b..3a2b7bc4a82 100644 --- a/llvm/test/CodeGen/X86/fmul-combines.ll +++ b/llvm/test/CodeGen/X86/fmul-combines.ll @@ -76,12 +76,12 @@ define <4 x float> @constant_fold_fmul_v4f32_undef(<4 x float> %x) { ret <4 x float> %y } -define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 { -; CHECK-LABEL: fmul0_v4f32: +define <4 x float> @fmul0_v4f32_nsz_nnan(<4 x float> %x) #0 { +; CHECK-LABEL: fmul0_v4f32_nsz_nnan: ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0> + %y = fmul nnan nsz <4 x float> %x, <float 0.0, float 0.0, float 0.0, float 0.0> ret <4 x float> %y } @@ -90,7 +90,7 @@ define <4 x float> @fmul0_v4f32_undef(<4 x float> %x) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, <float undef, float 0.0, float undef, float 0.0> + %y = fmul nnan nsz <4 x float> %x, <float undef, float 0.0, float undef, float 0.0> ret <4 x float> %y } diff --git a/llvm/test/CodeGen/X86/fp-fast.ll b/llvm/test/CodeGen/X86/fp-fast.ll index 7abedfd2d17..81dd983d94c 100644 --- a/llvm/test/CodeGen/X86/fp-fast.ll +++ b/llvm/test/CodeGen/X86/fp-fast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math --enable-no-nans-fp-math < %s | FileCheck %s define float @test1(float %a) { ; CHECK-LABEL: test1: |
