[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

llvm-svn: 239161

5 files changed, 20 insertions, 87 deletions

diff --git a/llvm/test/CodeGen/Hexagon/args.ll b/llvm/test/CodeGen/Hexagon/args.ll
index aea4ffe2eee..1c470f68aa2 100644
--- a/llvm/test/CodeGen/Hexagon/args.ll
+++ b/llvm/test/CodeGen/Hexagon/args.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
-; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
-; CHECK: r1:0 = combine(#2, #1)
-; CHECK: r3:2 = combine(#4, #3)
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: r5:4 = combine(#6, #5)
+; CHECK: r3:2 = combine(#4, #3)
+; CHECK: r1:0 = combine(#2, #1)
+; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
 
 
 define void @foo() nounwind {
diff --git a/llvm/test/CodeGen/Hexagon/calling-conv.ll b/llvm/test/CodeGen/Hexagon/calling-conv.ll
deleted file mode 100644
index 7133c1ae7aa..00000000000
--- a/llvm/test/CodeGen/Hexagon/calling-conv.ll
+++ /dev/null
@@ -1,73 +0,0 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
-; RUN:   FileCheck %s --check-prefix=CHECK-ONE
-; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
-; RUN:   FileCheck %s --check-prefix=CHECK-TWO
-; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
-; RUN:   FileCheck %s --check-prefix=CHECK-THREE
-
-%struct.test_struct = type { i32, i8, i64 }
-%struct.test_struct_long = type { i8, i64 }
-
-@mystruct = external global %struct.test_struct*, align 4
-
-; CHECK-ONE:    memw(r29+#48) = r2
-; CHECK-TWO:    memw(r29+#52) = r2
-; CHECK-THREE:  memw(r29+#56) = r2
-; Function Attrs: nounwind
-define void @foo(%struct.test_struct* noalias sret %agg.result, i32 %a, i8 zeroext %c, %struct.test_struct* byval %s, %struct.test_struct_long* byval %t) #0 {
-entry:
-  %a.addr = alloca i32, align 4
-  %c.addr = alloca i8, align 1
-  %z = alloca i32, align 4
-  %ret = alloca %struct.test_struct, align 8
-  store i32 %a, i32* %a.addr, align 4
-  store i8 %c, i8* %c.addr, align 1
-  %0 = bitcast i32* %z to i8*
-  call void @llvm.lifetime.start(i64 4, i8* %0) #1
-  store i32 45, i32* %z, align 4
-  %1 = bitcast %struct.test_struct* %ret to i8*
-  call void @llvm.lifetime.start(i64 16, i8* %1) #1
-  %2 = load i32, i32* %z, align 4
-  %3 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
-  %4 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
-  %5 = load i8, i8* %c.addr, align 1
-  %6 = load i32, i32* %a.addr, align 4
-  %conv = sext i32 %6 to i64
-  %add = add nsw i64 %conv, 1
-  %7 = load i32, i32* %a.addr, align 4
-  %add1 = add nsw i32 %7, 2
-  %8 = load i32, i32* %a.addr, align 4
-  %conv2 = sext i32 %8 to i64
-  %add3 = add nsw i64 %conv2, 3
-  %9 = load i8, i8* %c.addr, align 1
-  %10 = load i8, i8* %c.addr, align 1
-  %11 = load i8, i8* %c.addr, align 1
-  %12 = load i32, i32* %z, align 4
-  call void @bar(%struct.test_struct* sret %ret, i32 %2, %struct.test_struct* byval %3, %struct.test_struct* byval %4, i8 zeroext %5, i64 %add, i32 %add1, i64 %add3, i8 zeroext %9, i8 zeroext %10, i8 zeroext %11, i32 %12)
-  %x = getelementptr inbounds %struct.test_struct, %struct.test_struct* %ret, i32 0, i32 0
-  store i32 20, i32* %x, align 4
-  %13 = bitcast %struct.test_struct* %agg.result to i8*
-  %14 = bitcast %struct.test_struct* %ret to i8*
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %13, i8* %14, i32 16, i32 8, i1 false)
-  %15 = bitcast %struct.test_struct* %ret to i8*
-  call void @llvm.lifetime.end(i64 16, i8* %15) #1
-  %16 = bitcast i32* %z to i8*
-  call void @llvm.lifetime.end(i64 4, i8* %16) #1
-  ret void
-}
-
-; Function Attrs: nounwind
-declare void @llvm.lifetime.start(i64, i8* nocapture) #1
-
-declare void @bar(%struct.test_struct* sret, i32, %struct.test_struct* byval, %struct.test_struct* byval, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) #2
-
-; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1
-
-; Function Attrs: nounwind
-declare void @llvm.lifetime.end(i64, i8* nocapture) #1
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind }
-attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
-
diff --git a/llvm/test/CodeGen/Hexagon/dualstore.ll b/llvm/test/CodeGen/Hexagon/dualstore.ll
index 33d9ce9b935..9f4569d6459 100644
--- a/llvm/test/CodeGen/Hexagon/dualstore.ll
+++ b/llvm/test/CodeGen/Hexagon/dualstore.ll
@@ -1,12 +1,11 @@
-; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s
+; RUN: llc -march=hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
 ; Check that we generate dual stores in one packet in V4
 
-; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
-; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
+; CHECK: 00 40 9f 52 529f4000
+; CHECK: 10 10 00 f0 f0001010
 
-define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind {
-entry:
-  store i32 %v, i32* %p1, align 4
-  store i32 %v, i32* %p2, align 4
-  ret i32 0
+define void @foo(i32* %a, i32* %b) {
+  store i32 0, i32* %a
+  store i32 0, i32* %b
+  ret void
 }
diff --git a/llvm/test/CodeGen/Hexagon/duplex.ll b/llvm/test/CodeGen/Hexagon/duplex.ll
new file mode 100644
index 00000000000..80fe61ceccc
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/duplex.ll
@@ -0,0 +1,7 @@
+; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
+
+; CHECK: c0 3f 00 48 48003fc0
+
+define i32 @foo() {
+ret i32 0
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/Hexagon/sube.ll b/llvm/test/CodeGen/Hexagon/sube.ll
index 873f52b2d5d..9735894c419 100644
--- a/llvm/test/CodeGen/Hexagon/sube.ll
+++ b/llvm/test/CodeGen/Hexagon/sube.ll
@@ -3,10 +3,10 @@
 ; CHECK: r{{[0-9]+:[0-9]+}} = #1
 ; CHECK: r{{[0-9]+:[0-9]+}} = #0
 ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
 ; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
 ; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
 ; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
 
 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {