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| author | Craig Topper <craig.topper@intel.com> | 2018-03-04 01:48:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-04 01:48:00 +0000 |
| commit | be31585be861e6503bf7401d469d201f707e3f70 (patch) | |
| tree | 10095de53390dfad1c3ef4e8c5ef4c80e11e1ff7 /llvm/test/CodeGen | |
| parent | 364b9c2adb633280509db32c7afe869e010c695f (diff) | |
| download | bcm5719-llvm-be31585be861e6503bf7401d469d201f707e3f70.tar.gz bcm5719-llvm-be31585be861e6503bf7401d469d201f707e3f70.zip | |
[X86] Lower v1i1/v2i1/v4i1/v8i1 load/stores to i8 load/store during op legalization if AVX512DQ is not supported.
We were previously doing this with isel patterns. Moving it to op legalization gives us chance to see the required bitcast earlier. And it lets us remove some isel patterns.
llvm-svn: 326669
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-mask-op.ll | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll index 88d5ed4f7ad..1038c90ab9d 100644 --- a/llvm/test/CodeGen/X86/avx512-mask-op.ll +++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll @@ -348,9 +348,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { define i8 @conv1(<8 x i1>* %R) { ; KNL-LABEL: conv1: ; KNL: ## %bb.0: ## %entry -; KNL-NEXT: kxnorw %k0, %k0, %k0 -; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: movb %al, (%rdi) +; KNL-NEXT: movb $-1, (%rdi) ; KNL-NEXT: movb $-2, -{{[0-9]+}}(%rsp) ; KNL-NEXT: movb $-2, %al ; KNL-NEXT: retq @@ -365,9 +363,7 @@ define i8 @conv1(<8 x i1>* %R) { ; ; AVX512BW-LABEL: conv1: ; AVX512BW: ## %bb.0: ## %entry -; AVX512BW-NEXT: kxnorw %k0, %k0, %k0 -; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: movb %al, (%rdi) +; AVX512BW-NEXT: movb $-1, (%rdi) ; AVX512BW-NEXT: movb $-2, -{{[0-9]+}}(%rsp) ; AVX512BW-NEXT: movb $-2, %al ; AVX512BW-NEXT: retq |
