diff options
| author | QingShan Zhang <qshanz@cn.ibm.com> | 2019-10-11 08:36:54 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2019-10-11 08:36:54 +0000 |
| commit | bb8d54001075ed22fc63d366e33c3fcdfa3fd3e0 (patch) | |
| tree | 884347f1535fd165bde364fcc8e2c8236e0636a2 /llvm/test/CodeGen | |
| parent | e0cb1cf7e3689bdd48ef996da1780819ebc60bc0 (diff) | |
| download | bcm5719-llvm-bb8d54001075ed22fc63d366e33c3fcdfa3fd3e0.tar.gz bcm5719-llvm-bb8d54001075ed22fc63d366e33c3fcdfa3fd3e0.zip | |
[TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel
Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like:
llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, -1,...
};
llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, -1,...
InstB, 0,...
};
The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now:
llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, 0,...
};
llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, 0,...
InstB, 0,...
};
And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB.
Differential Revision: https://reviews.llvm.org/D67950
llvm-svn: 374524
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll index c72d4584537..16d0216df7e 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll @@ -45,7 +45,6 @@ entry: ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp -; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: bne .LBB0_1 for.body: |
