diff options
| -rw-r--r-- | llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 | ||||
| -rw-r--r-- | llvm/test/TableGen/InvalidMCSchedClassDesc.td | 47 | ||||
| -rw-r--r-- | llvm/utils/TableGen/SubtargetEmitter.cpp | 1 |
3 files changed, 48 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll index c72d4584537..16d0216df7e 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll @@ -45,7 +45,6 @@ entry: ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp -; CHECK-REG-PRESSURE: ldr{{.*}}, [sp ; CHECK-REG-PRESSURE: bne .LBB0_1 for.body: diff --git a/llvm/test/TableGen/InvalidMCSchedClassDesc.td b/llvm/test/TableGen/InvalidMCSchedClassDesc.td new file mode 100644 index 00000000000..f1b4ed00a6a --- /dev/null +++ b/llvm/test/TableGen/InvalidMCSchedClassDesc.td @@ -0,0 +1,47 @@ +// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s +// Check if it is valid MCSchedClassDesc if didn't have the resources. + +include "llvm/Target/Target.td" + +def MyTarget : Target; + +let OutOperandList = (outs), InOperandList = (ins) in { + def Inst_A : Instruction; + def Inst_B : Instruction; +} + +let CompleteModel = 0 in { + def SchedModel_A: SchedMachineModel; + def SchedModel_B: SchedMachineModel; + def SchedModel_C: SchedMachineModel; +} + +// Inst_B didn't have the resoures, and it is invalid. +// CHECK: SchedModel_ASchedClasses[] = { +// CHECK: {DBGFIELD("Inst_A") 1 +// CHECK-NEXT: {DBGFIELD("Inst_B") 16383 +let SchedModel = SchedModel_A in { + def Write_A : SchedWriteRes<[]>; + def : InstRW<[Write_A], (instrs Inst_A)>; +} + +// Inst_A didn't have the resoures, and it is invalid. +// CHECK: SchedModel_BSchedClasses[] = { +// CHECK: {DBGFIELD("Inst_A") 16383 +// CHECK-NEXT: {DBGFIELD("Inst_B") 1 +let SchedModel = SchedModel_B in { + def Write_B: SchedWriteRes<[]>; + def : InstRW<[Write_B], (instrs Inst_B)>; +} + +// CHECK: SchedModel_CSchedClasses[] = { +// CHECK: {DBGFIELD("Inst_A") 1 +// CHECK-NEXT: {DBGFIELD("Inst_B") 1 +let SchedModel = SchedModel_C in { + def Write_C: SchedWriteRes<[]>; + def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>; +} + +def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>; +def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>; +def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>; diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index f9705723650..9b094adb7d5 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -1057,6 +1057,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, LLVM_DEBUG(dbgs() << ProcModel.ModelName << " does not have resources for class " << SC.Name << '\n'); + SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; } } // Sum resources across all operand writes. |
