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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-09 17:54:51 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-09 17:54:51 +0000 |
| commit | b25f60210ffff9ea26b47984c02560b04094626f (patch) | |
| tree | c3a9431d865c57b587e22ba38a75787a566795c3 /llvm/test/CodeGen | |
| parent | 7bcf46e29dd47a3f0bb872f12022fa6fc44e5351 (diff) | |
| download | bcm5719-llvm-b25f60210ffff9ea26b47984c02560b04094626f.tar.gz bcm5719-llvm-b25f60210ffff9ea26b47984c02560b04094626f.zip | |
[X86][BMI2] Regenerate mulx tests
llvm-svn: 294598
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/mulx32.ll | 21 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/mulx64.ll | 20 |
2 files changed, 27 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/X86/mulx32.ll b/llvm/test/CodeGen/X86/mulx32.ll index 42ef2eb6f64..9ebd380170d 100644 --- a/llvm/test/CodeGen/X86/mulx32.ll +++ b/llvm/test/CodeGen/X86/mulx32.ll @@ -1,22 +1,29 @@ -; RUN: llc -mcpu=core-avx2 -march=x86 < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown -mattr=+bmi2 | FileCheck %s +; RUN: llc < %s -mtriple=i686-unknown -mcpu=core-avx2 | FileCheck %s define i64 @f1(i32 %a, i32 %b) { +; CHECK-LABEL: f1: +; CHECK: # BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx +; CHECK-NEXT: mulxl {{[0-9]+}}(%esp), %eax, %edx +; CHECK-NEXT: retl %x = zext i32 %a to i64 %y = zext i32 %b to i64 %r = mul i64 %x, %y -; CHECK: f1 -; CHECK: mulxl -; CHECK: ret ret i64 %r } define i64 @f2(i32 %a, i32* %p) { +; CHECK-LABEL: f2: +; CHECK: # BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx +; CHECK-NEXT: mulxl (%eax), %eax, %edx +; CHECK-NEXT: retl %b = load i32, i32* %p %x = zext i32 %a to i64 %y = zext i32 %b to i64 %r = mul i64 %x, %y -; CHECK: f2 -; CHECK: mulxl ({{.+}}), %{{.+}}, %{{.+}} -; CHECK: ret ret i64 %r } diff --git a/llvm/test/CodeGen/X86/mulx64.ll b/llvm/test/CodeGen/X86/mulx64.ll index 808c02290b7..7cc10e017fc 100644 --- a/llvm/test/CodeGen/X86/mulx64.ll +++ b/llvm/test/CodeGen/X86/mulx64.ll @@ -1,22 +1,28 @@ -; RUN: llc -mcpu=core-avx2 -march=x86-64 < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+bmi2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s define i128 @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: # BB#0: +; CHECK-NEXT: movq %rdi, %rdx +; CHECK-NEXT: mulxq %rsi, %rax, %rdx +; CHECK-NEXT: retq %x = zext i64 %a to i128 %y = zext i64 %b to i128 %r = mul i128 %x, %y -; CHECK: f1 -; CHECK: mulxq -; CHECK: ret ret i128 %r } define i128 @f2(i64 %a, i64* %p) { +; CHECK-LABEL: f2: +; CHECK: # BB#0: +; CHECK-NEXT: movq %rdi, %rdx +; CHECK-NEXT: mulxq (%rsi), %rax, %rdx +; CHECK-NEXT: retq %b = load i64, i64* %p %x = zext i64 %a to i128 %y = zext i64 %b to i128 %r = mul i128 %x, %y -; CHECK: f2 -; CHECK: mulxq ({{.+}}), %{{.+}}, %{{.+}} -; CHECK: ret ret i128 %r } |
