Code size optimisation: don't expand a div to a mul and and a shift sequence.

As a result, the urem instruction will not be expanded to a sequence of umull,
lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod.

Differential Revision: http://reviews.llvm.org/D22131

llvm-svn: 274843

1 files changed, 25 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/urem-opt-size.ll b/llvm/test/CodeGen/ARM/urem-opt-size.ll
new file mode 100644
index 00000000000..4490a47093e
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/urem-opt-size.ll
@@ -0,0 +1,25 @@
+; When optimising for size, we don't want to expand a div to a mul and
+; and a shift sequence. As a result, the urem instruction will not be
+; expanded to a sequence of umull, lsrs, muls and sub instructions, but
+; just a call to __aeabi_uidivmod.
+;
+; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv7m-arm-none-eabi"
+
+define i32 @foo() local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: foo:
+; CHECK: __aeabi_uidivmod
+; CHECK-NOT: umull
+  %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+  %rem = urem i32 %call, 1000000
+  %cmp = icmp eq i32 %rem, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+declare i32 @GetValue(...) local_unnamed_addr
+
+attributes #0 = { minsize nounwind optsize }