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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 10:25:47 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 10:25:47 +0000 |
| commit | 68b38866786033b17d71d8b93b0c10c8c3d3cc9b (patch) | |
| tree | cf56fe99b02b4bc2ccfca75ef15efa368022bcf7 /llvm/test/CodeGen | |
| parent | 8f306a779b6481a60d708ba403dc8c5bede06ae6 (diff) | |
| download | bcm5719-llvm-68b38866786033b17d71d8b93b0c10c8c3d3cc9b.tar.gz bcm5719-llvm-68b38866786033b17d71d8b93b0c10c8c3d3cc9b.zip | |
Add preliminary v2f32 support for SPU. Like with v2i32, we just
duplicate the instructions and operate on half vectors.
Also reorder code in SPUInstrInfo.td for better coherency.
llvm-svn: 110037
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/v2f32.ll | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/CellSPU/v2f32.ll b/llvm/test/CodeGen/CellSPU/v2f32.ll new file mode 100644 index 00000000000..2631777511d --- /dev/null +++ b/llvm/test/CodeGen/CellSPU/v2f32.ll @@ -0,0 +1,35 @@ +;RUN: llc --march=cellspu %s -o - | FileCheck %s +%vec = type <2 x float> + +define %vec @test_ret(%vec %param) +{ +;CHECK: bi $lr + ret %vec %param +} + +define %vec @test_add(%vec %param) +{ +;CHECK: fa $3, $3, $3 + %1 = fadd %vec %param, %param +;CHECK: bi $lr + ret %vec %1 +} + +define %vec @test_sub(%vec %param) +{ +;CHECK: fs $3, $3, $3 + %1 = fsub %vec %param, %param + +;CHECK: bi $lr + ret %vec %1 +} + +define %vec @test_mul(%vec %param) +{ +;CHECK: fm $3, $3, $3 + %1 = fmul %vec %param, %param + +;CHECK: bi $lr + ret %vec %1 +} + |
