From 68b38866786033b17d71d8b93b0c10c8c3d3cc9b Mon Sep 17 00:00:00 2001
From: Kalle Raiskila <kalle.raiskila@nokia.com>
Date: Mon, 2 Aug 2010 10:25:47 +0000
Subject: Add preliminary v2f32 support for SPU. Like with v2i32, we just
 duplicate the instructions and operate on half vectors.

Also reorder code in SPUInstrInfo.td for better coherency.

llvm-svn: 110037
---
 llvm/test/CodeGen/CellSPU/v2f32.ll | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 llvm/test/CodeGen/CellSPU/v2f32.ll

(limited to 'llvm/test/CodeGen')

diff --git a/llvm/test/CodeGen/CellSPU/v2f32.ll b/llvm/test/CodeGen/CellSPU/v2f32.ll
new file mode 100644
index 00000000000..2631777511d
--- /dev/null
+++ b/llvm/test/CodeGen/CellSPU/v2f32.ll
@@ -0,0 +1,35 @@
+;RUN: llc --march=cellspu %s -o - | FileCheck %s
+%vec = type <2 x float>
+
+define %vec @test_ret(%vec %param)
+{
+;CHECK: bi $lr
+ ret %vec %param
+}
+
+define %vec @test_add(%vec %param)
+{
+;CHECK: fa $3, $3, $3
+ %1 = fadd %vec %param, %param
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_sub(%vec %param)
+{
+;CHECK: fs $3, $3, $3
+ %1 = fsub %vec %param, %param
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_mul(%vec %param)
+{
+;CHECK: fm $3, $3, $3
+ %1 = fmul %vec %param, %param
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
-- 
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