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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-07-21 17:51:27 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-07-21 17:51:27 +0000 |
| commit | 3ad0d01e9e7c71a9de714380f232b45d7c8147fe (patch) | |
| tree | 5e296f1c815067bbad3cc9a862245161651eacb3 /llvm/test/CodeGen | |
| parent | 1dec57d5b0fb6b7044c9afa80e7c3b6295d36fd3 (diff) | |
| download | bcm5719-llvm-3ad0d01e9e7c71a9de714380f232b45d7c8147fe.tar.gz bcm5719-llvm-3ad0d01e9e7c71a9de714380f232b45d7c8147fe.zip | |
[Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")
llvm-svn: 308761
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/inline-asm-a.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-a.ll b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll new file mode 100644 index 00000000000..08862d9233a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that constraint a is handled correctly. +; CHECK: [[M:m[01]]] = r1 +; CHECK: memw(r0++[[M]]) = r2 + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @foo(i32* %a, i32 %m, i32 %v) #0 { +entry: + tail call void asm sideeffect "memw($0++$1) = $2", "r,a,r,~{memory}"(i32* %a, i32 %m, i32 %v) + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" } |
