diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/inline-asm-a.ll | 16 |
2 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 1291af86c7e..f02cd6d3992 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2923,7 +2923,11 @@ HexagonTargetLowering::getConstraintType(StringRef Constraint) const { case 'q': case 'v': if (Subtarget.useHVXOps()) - return C_Register; + return C_RegisterClass; + break; + case 'a': + return C_RegisterClass; + default: break; } } @@ -2951,6 +2955,9 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( case MVT::f64: return std::make_pair(0U, &Hexagon::DoubleRegsRegClass); } + break; + case 'a': // M0-M1 + return std::make_pair(0U, &Hexagon::ModRegsRegClass); case 'q': // q0-q3 switch (VT.getSizeInBits()) { default: @@ -2960,6 +2967,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( case 1024: return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass); } + break; case 'v': // V0-V31 switch (VT.getSizeInBits()) { default: @@ -2973,7 +2981,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( case 2048: return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass); } - + break; default: llvm_unreachable("Unknown asm register class"); } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-a.ll b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll new file mode 100644 index 00000000000..08862d9233a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that constraint a is handled correctly. +; CHECK: [[M:m[01]]] = r1 +; CHECK: memw(r0++[[M]]) = r2 + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @foo(i32* %a, i32 %m, i32 %v) #0 { +entry: + tail call void asm sideeffect "memw($0++$1) = $2", "r,a,r,~{memory}"(i32* %a, i32 %m, i32 %v) + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" } |
