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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2012-11-13 18:40:58 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2012-11-13 18:40:58 +0000
commit3946877f8835b50e67d55f6a807e62a1969e0fc3 (patch)
treeb79f7b9fc27707ef5214cd33effe70b88041501e /llvm/test/CodeGen
parent70b4dcfbcd1f388b8dc8adef8c175a4924fa0121 (diff)
downloadbcm5719-llvm-3946877f8835b50e67d55f6a807e62a1969e0fc3.tar.gz
bcm5719-llvm-3946877f8835b50e67d55f6a807e62a1969e0fc3.zip
Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll b/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll
new file mode 100644
index 00000000000..41533a8f322
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @test(i64 %n) nounwind {
+entry:
+ %0 = alloca i8, i64 %n, align 1
+ %1 = alloca i8, i64 %n, align 1
+ call void @use(i8* %0, i8* %1) nounwind
+ ret void
+}
+
+declare void @use(i8*, i8*)
+
+; Check we actually have two instances of dynamic stack allocation,
+; identified by the stdux used to update the back-chain link.
+; CHECK: stdux
+; CHECK: stdux
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