From 3946877f8835b50e67d55f6a807e62a1969e0fc3 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Tue, 13 Nov 2012 18:40:58 +0000 Subject: Do not consider a machine instruction that uses and defines the same physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855 --- llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll (limited to 'llvm/test/CodeGen') diff --git a/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll b/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll new file mode 100644 index 00000000000..41533a8f322 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @test(i64 %n) nounwind { +entry: + %0 = alloca i8, i64 %n, align 1 + %1 = alloca i8, i64 %n, align 1 + call void @use(i8* %0, i8* %1) nounwind + ret void +} + +declare void @use(i8*, i8*) + +; Check we actually have two instances of dynamic stack allocation, +; identified by the stdux used to update the back-chain link. +; CHECK: stdux +; CHECK: stdux -- cgit v1.2.3