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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 19:16:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 19:16:52 +0000 |
| commit | 06cbb27a792f5422b89c1c01fb17f37f4de048d6 (patch) | |
| tree | 2e3fd4c260148c374ab29fac49901dbbcad39d2e /llvm/test/CodeGen | |
| parent | cc6238158a7dfb301a7a671fb5a70ebb51af2cde (diff) | |
| download | bcm5719-llvm-06cbb27a792f5422b89c1c01fb17f37f4de048d6.tar.gz bcm5719-llvm-06cbb27a792f5422b89c1c01fb17f37f4de048d6.zip | |
AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF
Patch by Tom Stellard
llvm-svn: 326470
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir index d0499e06806..cc68b86cf89 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir @@ -1,31 +1,52 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -o - | FileCheck %s # Check the default mappings for various instructions. --- -# CHECK-LABEL: name: test_fconstant_f32_1 name: test_fconstant_f32_1 legalized: true body: | bb.0: - ; CHECK: %0:sgpr(s32) = G_FCONSTANT float 1.0 + ; CHECK-LABEL: name: test_fconstant_f32_1 + ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 %0:_(s32) = G_FCONSTANT float 1.0 ... --- -# CHECK-LABEL: name: test_fconstant_f64_1 name: test_fconstant_f64_1 legalized: true body: | bb.0: - ; CHECK: %0:sgpr(s64) = G_FCONSTANT double 1.0 + ; CHECK-LABEL: name: test_fconstant_f64_1 + ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 1.000000e+00 %0:_(s64) = G_FCONSTANT double 1.0 ... --- -# CHECK-LABEL: name: test_fconstant_f16_1 name: test_fconstant_f16_1 legalized: true body: | bb.0: - ; CHECK: %0:sgpr(s32) = G_FCONSTANT half 0xH3C00 + ; CHECK-LABEL: name: test_fconstant_f16_1 + ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT half 0xH3C00 %0:_(s32) = G_FCONSTANT half 1.0 ... + +--- +name: test_implicit_def_s32 +legalized: true +body: | + bb.0: + ; CHECK-LABEL: name: test_implicit_def_s32 + ; CHECK: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF + %0:_(s32) = G_IMPLICIT_DEF +... + +--- +name: test_implicit_def_s64 +legalized: true +body: | + bb.0: + ; CHECK-LABEL: name: test_implicit_def_s64 + ; CHECK: [[DEF:%[0-9]+]]:sgpr(s64) = G_IMPLICIT_DEF + %0:_(s64) = G_IMPLICIT_DEF +... |
