AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF

Patch by Tom Stellard

llvm-svn: 326470

3 files changed, 35 insertions, 6 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 35aa373138f..ae193fec7d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -54,6 +54,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
   setAction({G_FCONSTANT, S32}, Legal);
   setAction({G_FCONSTANT, S64}, Legal);
 
+  setAction({G_IMPLICIT_DEF, S32}, Legal);
+  setAction({G_IMPLICIT_DEF, S64}, Legal);
+
   setAction({G_FADD, S32}, Legal);
 
   setAction({G_FCMP, S1}, Legal);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 4454e5056e3..8d94898415b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -174,6 +174,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   default:
     IsComplete = false;
     break;
+  case AMDGPU::G_IMPLICIT_DEF: {
+    unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+    OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
+    break;
+  }
   case AMDGPU::G_FCONSTANT:
   case AMDGPU::G_CONSTANT: {
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index d0499e06806..cc68b86cf89 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -1,31 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
 
 # Check the default mappings for various instructions.
 
 ---
-# CHECK-LABEL: name: test_fconstant_f32_1
 name:            test_fconstant_f32_1
 legalized:       true
 body: |
   bb.0:
-    ; CHECK: %0:sgpr(s32) = G_FCONSTANT float 1.0
+    ; CHECK-LABEL: name: test_fconstant_f32_1
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
     %0:_(s32) = G_FCONSTANT float 1.0
 ...
 ---
-# CHECK-LABEL: name: test_fconstant_f64_1
 name:            test_fconstant_f64_1
 legalized:       true
 body: |
   bb.0:
-    ; CHECK: %0:sgpr(s64) = G_FCONSTANT double 1.0
+    ; CHECK-LABEL: name: test_fconstant_f64_1
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 1.000000e+00
     %0:_(s64) = G_FCONSTANT double 1.0
 ...
 ---
-# CHECK-LABEL: name: test_fconstant_f16_1
 name:            test_fconstant_f16_1
 legalized:       true
 body: |
   bb.0:
-    ; CHECK: %0:sgpr(s32) = G_FCONSTANT half 0xH3C00
+    ; CHECK-LABEL: name: test_fconstant_f16_1
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT half 0xH3C00
     %0:_(s32) = G_FCONSTANT half 1.0
 ...
+
+---
+name:            test_implicit_def_s32
+legalized:       true
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: test_implicit_def_s32
+    ; CHECK: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+    %0:_(s32) = G_IMPLICIT_DEF
+...
+
+---
+name:            test_implicit_def_s64
+legalized:       true
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: test_implicit_def_s64
+    ; CHECK: [[DEF:%[0-9]+]]:sgpr(s64) = G_IMPLICIT_DEF
+    %0:_(s64) = G_IMPLICIT_DEF
+...