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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-07-31 19:50:45 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-07-31 19:50:45 +0000 |
| commit | 6be48e4aa70c50d58b9759187e8f601a2da7b23c (patch) | |
| tree | f4c648ece065a63d761bf8c761c599cc36f7df2d /llvm/test/CodeGen/X86/shift-double.ll | |
| parent | 600495266100380fd7152feb7333b0353ce839b7 (diff) | |
| download | bcm5719-llvm-6be48e4aa70c50d58b9759187e8f601a2da7b23c.tar.gz bcm5719-llvm-6be48e4aa70c50d58b9759187e8f601a2da7b23c.zip | |
[X86] Improve 64-bit shifts on 32-bit targets (PR14593)
As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.
Differential Revision: https://reviews.llvm.org/D23000
llvm-svn: 277299
Diffstat (limited to 'llvm/test/CodeGen/X86/shift-double.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/shift-double.ll | 91 |
1 files changed, 24 insertions, 67 deletions
diff --git a/llvm/test/CodeGen/X86/shift-double.ll b/llvm/test/CodeGen/X86/shift-double.ll index 0cb6a575255..ba9baea9862 100644 --- a/llvm/test/CodeGen/X86/shift-double.ll +++ b/llvm/test/CodeGen/X86/shift-double.ll @@ -151,19 +151,13 @@ define i64 @test8(i64 %val, i32 %bits) nounwind { ; CHECK-LABEL: test8: ; CHECK: # BB#0: ; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movb {{[0-9]+}}(%esp), %ch -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi -; CHECK-NEXT: movb %ch, %cl -; CHECK-NEXT: shll %cl, %esi -; CHECK-NEXT: movl %eax, %edx -; CHECK-NEXT: shrl %edx -; CHECK-NEXT: andb $31, %cl -; CHECK-NEXT: xorb $31, %cl -; CHECK-NEXT: shrl %cl, %edx -; CHECK-NEXT: orl %esi, %edx -; CHECK-NEXT: movb %ch, %cl +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx +; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: shll %cl, %eax +; CHECK-NEXT: andb $31, %cl +; CHECK-NEXT: shldl %cl, %esi, %edx ; CHECK-NEXT: popl %esi ; CHECK-NEXT: retl %and = and i32 %bits, 31 @@ -176,18 +170,13 @@ define i64 @test9(i64 %val, i32 %bits) nounwind { ; CHECK-LABEL: test9: ; CHECK: # BB#0: ; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movb {{[0-9]+}}(%esp), %ch +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx -; CHECK-NEXT: movb %ch, %cl -; CHECK-NEXT: shrl %cl, %esi -; CHECK-NEXT: leal (%edx,%edx), %eax -; CHECK-NEXT: andb $31, %cl -; CHECK-NEXT: xorb $31, %cl -; CHECK-NEXT: shll %cl, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: movb %ch, %cl +; CHECK-NEXT: movl %esi, %edx ; CHECK-NEXT: sarl %cl, %edx +; CHECK-NEXT: andb $31, %cl +; CHECK-NEXT: shrdl %cl, %esi, %eax ; CHECK-NEXT: popl %esi ; CHECK-NEXT: retl %and = and i32 %bits, 31 @@ -200,18 +189,13 @@ define i64 @test10(i64 %val, i32 %bits) nounwind { ; CHECK-LABEL: test10: ; CHECK: # BB#0: ; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movb {{[0-9]+}}(%esp), %ch +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx -; CHECK-NEXT: movb %ch, %cl -; CHECK-NEXT: shrl %cl, %esi -; CHECK-NEXT: leal (%edx,%edx), %eax -; CHECK-NEXT: andb $31, %cl -; CHECK-NEXT: xorb $31, %cl -; CHECK-NEXT: shll %cl, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: movb %ch, %cl +; CHECK-NEXT: movl %esi, %edx ; CHECK-NEXT: shrl %cl, %edx +; CHECK-NEXT: andb $31, %cl +; CHECK-NEXT: shrdl %cl, %esi, %eax ; CHECK-NEXT: popl %esi ; CHECK-NEXT: retl %and = and i32 %bits, 31 @@ -291,19 +275,10 @@ define i32 @test14(i32 %hi, i32 %lo, i32 %bits) nounwind { define i32 @test15(i32 %hi, i32 %lo, i32 %bits) nounwind { ; CHECK-LABEL: test15: ; CHECK: # BB#0: -; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: xorl $31, %ecx -; CHECK-NEXT: shrl %esi -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> -; CHECK-NEXT: shrl %cl, %esi -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: shll %cl, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: popl %esi +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: shldl %cl, %edx, %eax ; CHECK-NEXT: retl %bits32 = xor i32 %bits, 31 %lo2 = lshr i32 %lo, 1 @@ -316,19 +291,10 @@ define i32 @test15(i32 %hi, i32 %lo, i32 %bits) nounwind { define i32 @test16(i32 %hi, i32 %lo, i32 %bits) nounwind { ; CHECK-LABEL: test16: ; CHECK: # BB#0: -; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: xorl $31, %ecx -; CHECK-NEXT: addl %esi, %esi -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> -; CHECK-NEXT: shll %cl, %esi -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: shrl %cl, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: popl %esi +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: shrdl %cl, %edx, %eax ; CHECK-NEXT: retl %bits32 = xor i32 %bits, 31 %lo2 = shl i32 %lo, 1 @@ -341,19 +307,10 @@ define i32 @test16(i32 %hi, i32 %lo, i32 %bits) nounwind { define i32 @test17(i32 %hi, i32 %lo, i32 %bits) nounwind { ; CHECK-LABEL: test17: ; CHECK: # BB#0: -; CHECK-NEXT: pushl %esi -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: xorl $31, %ecx -; CHECK-NEXT: addl %esi, %esi -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> -; CHECK-NEXT: shll %cl, %esi -; CHECK-NEXT: movl %edx, %ecx -; CHECK-NEXT: shrl %cl, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: popl %esi +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: shrdl %cl, %edx, %eax ; CHECK-NEXT: retl %bits32 = xor i32 %bits, 31 %lo2 = add i32 %lo, %lo |
