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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-19 18:59:08 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-19 18:59:08 +0000 |
| commit | 2d0f20cc043458c945e4959c5b130c07a7f5b8b5 (patch) | |
| tree | 4c6c2685582012433738444bea2cce36c82c7b04 /llvm/test/CodeGen/X86/divrem8_ext.ll | |
| parent | 894c39f770298e8972d3518c9b3531b59c819f56 (diff) | |
| download | bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.tar.gz bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.zip | |
[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86.
Original Patch by @jonpa:
While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.
Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.
Differential Revision: https://reviews.llvm.org/D38128
llvm-svn: 342578
Diffstat (limited to 'llvm/test/CodeGen/X86/divrem8_ext.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/divrem8_ext.ll | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/divrem8_ext.ll b/llvm/test/CodeGen/X86/divrem8_ext.ll index 313aa868500..b9b6e1e8a36 100644 --- a/llvm/test/CodeGen/X86/divrem8_ext.ll +++ b/llvm/test/CodeGen/X86/divrem8_ext.ll @@ -112,6 +112,7 @@ define signext i8 @test_sdivrem_sext_ah(i8 %x, i8 %y) { ; X64-LABEL: test_sdivrem_sext_ah: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: cbtw ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %ecx @@ -137,6 +138,7 @@ define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) { ; X64-LABEL: test_srem_sext_ah: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: cbtw ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %eax @@ -161,6 +163,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8 %y) { ; X64-LABEL: test_srem_noext_ah: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: cbtw ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %eax @@ -186,6 +189,7 @@ define i64 @test_srem_sext64_ah(i8 %x, i8 %y) { ; X64-LABEL: test_srem_sext64_ah: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: cbtw ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %eax |
