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| author | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
|---|---|---|
| committer | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
| commit | 48904e9452de81375bd55d830d08e51cc8f2ec7e (patch) | |
| tree | 870ff19fbb173ec430372a5abbf06d4b27bc3836 /llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir | |
| parent | d811d9115b0b2d004a568e8ebdb37ba0ea6397d1 (diff) | |
| download | bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.tar.gz bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.zip | |
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
Diffstat (limited to 'llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir')
| -rw-r--r-- | llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir index ea6bfa57628..3ee95929441 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -26,7 +26,7 @@ --- name: test_add_v32i8 # ALL-LABEL: name: test_add_v32i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -66,7 +66,7 @@ body: | --- name: test_add_v16i16 # ALL-LABEL: name: test_add_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -106,7 +106,7 @@ body: | --- name: test_add_v8i32 # ALL-LABEL: name: test_add_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -146,7 +146,7 @@ body: | --- name: test_add_v4i64 # ALL-LABEL: name: test_add_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: |
