[ARM] Select MVE add and sub

This adds the first few patterns for MVE code generation, adding simple integer
add and sub patterns.

Initial code by David Sherwood

Differential Revision: https://reviews.llvm.org/D63255

llvm-svn: 364627

1 files changed, 64 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
new file mode 100644
index 00000000000..b2a846b644c
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+
+define arm_aapcs_vfpcc <16 x i8> @add_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: add_int8_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add <16 x i8> %src1, %src2
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @add_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: add_int16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add <8 x i16> %src1, %src2
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @add_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: add_int32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = add nsw <4 x i32> %src1, %src2
+  ret <4 x i32> %0
+}
+
+
+define arm_aapcs_vfpcc <16 x i8> @sub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
+; CHECK-LABEL: sub_int8_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i8 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub <16 x i8> %src2, %src1
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @sub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
+; CHECK-LABEL: sub_int16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i16 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub <8 x i16> %src2, %src1
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @sub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
+; CHECK-LABEL: sub_int32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.i32 q0, q1, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = sub nsw <4 x i32> %src2, %src1
+  ret <4 x i32> %0
+}