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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
| commit | 84f54a3bc9067cf9b48584d3da4e71049c490cac (patch) | |
| tree | 10ea4c3bb4f265144293fc2918b51d04faa0ce48 /llvm/test/CodeGen/SystemZ/insert-02.ll | |
| parent | c8a53795ab3463d29950f25f6b91860ef43c502b (diff) | |
| download | bcm5719-llvm-84f54a3bc9067cf9b48584d3da4e71049c490cac.tar.gz bcm5719-llvm-84f54a3bc9067cf9b48584d3da4e71049c490cac.zip | |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
llvm-svn: 186072
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/insert-02.ll')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/insert-02.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/SystemZ/insert-02.ll b/llvm/test/CodeGen/SystemZ/insert-02.ll index 471889dede6..e9980144e9e 100644 --- a/llvm/test/CodeGen/SystemZ/insert-02.ll +++ b/llvm/test/CodeGen/SystemZ/insert-02.ll @@ -33,7 +33,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) { ; register value. We can use IC but must keep the original mask. define i64 @f3(i64 %orig, i8 *%ptr) { ; CHECK: f3: -; CHECK: nill %r2, 65024 +; CHECK: risbg %r2, %r2, 0, 182, 0 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 %val = load i8 *%ptr @@ -46,7 +46,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) { ; Like f3, but with the operands reversed. define i64 @f4(i64 %orig, i8 *%ptr) { ; CHECK: f4: -; CHECK: nill %r2, 65024 +; CHECK: risbg %r2, %r2, 0, 182, 0 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 %val = load i8 *%ptr |
