[RISCV] Machine Operand Flag Serialization

Summary:
These hooks ensure that the RISC-V backend can serialize and parse MIR
correctly.

Reviewers: jrtc27, luismarques

Reviewed By: luismarques

Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70666

1 files changed, 77 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/mir-target-flags.ll b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
new file mode 100644
index 00000000000..fcfdcfdb2b4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
@@ -0,0 +1,77 @@
+; RUN: llc -mtriple=riscv32 --code-model=small \
+; RUN:    -stop-after riscv-expand-pseudo %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
+; RUN:   FileCheck %s -check-prefix=RV32-SMALL
+;
+; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
+; RUN:   -stop-after riscv-expand-pseudo %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
+; RUN:   FileCheck %s -check-prefix=RV32-MED
+
+; This tests the RISC-V-specific serialization and deserialization of
+; `target-flags(...)`
+
+@g_e = external global i32
+@g_i = internal global i32 0
+@t_un = external thread_local global i32
+@t_ld = external thread_local(localdynamic) global i32
+@t_ie = external thread_local(initialexec) global i32
+@t_le = external thread_local(localexec) global i32
+
+declare i32 @callee(i32) nounwind
+
+define i32 @caller(i32 %a) nounwind {
+; RV32-SMALL-LABEL: name: caller
+; RV32-SMALL:      target-flags(riscv-hi) @g_e
+; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_e
+; RV32-SMALL-NEXT: target-flags(riscv-hi) @g_i
+; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_i
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-hi) @t_un
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_un
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_un
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-hi) @t_ld
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_ld
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_ld
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-hi) @t_ie
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_ie
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_ie
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-hi) @t_le
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le
+; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le
+; RV32-SMALL:      target-flags(riscv-call) @callee
+;
+; RV32-MED-LABEL: name: caller
+; RV32-MED:      target-flags(riscv-got-hi) @g_e
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.1
+; RV32-MED:      target-flags(riscv-pcrel-hi) @g_i
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.2
+; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_un
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.3
+; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_ld
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.4
+; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED:      target-flags(riscv-tls-got-hi) @t_ie
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.5
+; RV32-MED:      target-flags(riscv-tprel-hi) @t_le
+; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
+; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
+; RV32-MED:      target-flags(riscv-plt) @callee
+;
+  %b = load i32, i32* @g_e
+  %c = load i32, i32* @g_i
+  %d = load i32, i32* @t_un
+  %e = load i32, i32* @t_ld
+  %f = load i32, i32* @t_ie
+  %g = load i32, i32* @t_le
+  %sum = bitcast i32 0 to i32
+  %sum.a = add i32 %sum, %a
+  %sum.b = add i32 %sum.a, %b
+  %sum.c = add i32 %sum.b, %c
+  %sum.d = add i32 %sum.c, %d
+  %sum.e = add i32 %sum.d, %e
+  %sum.f = add i32 %sum.e, %f
+  %sum.g = add i32 %sum.f, %g
+  %retval = call i32 @callee(i32 %sum.g)
+  ret i32 %retval
+}