[RISCV] Support stack offset exceed 32-bit for RV64

Differential Revision: https://reviews.llvm.org/D61884

llvm-svn: 371810

2 files changed, 59 insertions, 33 deletions

diff --git a/llvm/test/CodeGen/RISCV/rv64-large-stack.ll b/llvm/test/CodeGen/RISCV/rv64-large-stack.ll
new file mode 100644
index 00000000000..bf862ac52aa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-large-stack.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+;
+; The test case check that RV64 could handle the stack adjustment offset exceed
+; 32-bit.
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a0, 95
+; CHECK-NEXT:    addiw a0, a0, 1505
+; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    addi a0, a0, 32
+; CHECK-NEXT:    sub sp, sp, a0
+; CHECK-NEXT:    lui a0, 781250
+; CHECK-NEXT:    addiw a0, a0, 24
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    sd ra, 0(a0)
+; CHECK-NEXT:    addi a0, sp, 16
+; CHECK-NEXT:    call baz
+; CHECK-NEXT:    lui a0, 781250
+; CHECK-NEXT:    addiw a0, a0, 24
+; CHECK-NEXT:    add a0, sp, a0
+; CHECK-NEXT:    ld ra, 0(a0)
+; CHECK-NEXT:    lui a0, 95
+; CHECK-NEXT:    addiw a0, a0, 1505
+; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    addi a0, a0, 32
+; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    ret
+entry:
+  %w = alloca [100000000 x { fp128, fp128 }], align 16
+  %arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
+  call void @baz({ fp128, fp128 }* nonnull %arraydecay)
+  ret void
+}
+
+declare void @baz({ fp128, fp128 }*)
diff --git a/llvm/test/CodeGen/RISCV/stack-realignment.ll b/llvm/test/CodeGen/RISCV/stack-realignment.ll
index 252a099d098..dd06d6f0bff 100644
--- a/llvm/test/CodeGen/RISCV/stack-realignment.ll
+++ b/llvm/test/CodeGen/RISCV/stack-realignment.ll
@@ -348,38 +348,38 @@ define void @caller1024() nounwind {
 ; RV64I-LABEL: caller1024:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
+; RV64I-NEXT:    addiw a0, a0, -1032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
+; RV64I-NEXT:    addiw a0, a0, -1040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -1024
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1040
+; RV64I-NEXT:    addiw a0, a0, -1040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1032
+; RV64I-NEXT:    addiw a0, a0, -1032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addiw a0, a0, -1024
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 1024
@@ -431,7 +431,6 @@ define void @caller2048() nounwind {
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    andi sp, sp, -2048
 ; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
@@ -454,38 +453,37 @@ define void @caller2048() nounwind {
 ; RV64I-LABEL: caller2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addiw a0, a0, 2040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addiw a0, a0, 2032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    andi sp, sp, -2048
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2032
+; RV64I-NEXT:    addiw a0, a0, 2032
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addi a0, a0, 2040
+; RV64I-NEXT:    addiw a0, a0, 2040
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    addiw a0, a0, -2048
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 2048
@@ -522,7 +520,6 @@ define void @caller4096() nounwind {
 ; RV32I-LABEL: caller4096:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -4
@@ -533,17 +530,14 @@ define void @caller4096() nounwind {
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    sw s0, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add s0, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
 ; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    addi a0, a0, -8
@@ -554,46 +548,40 @@ define void @caller4096() nounwind {
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    lw ra, 0(a0)
 ; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: caller4096:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, sp, a0
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -8
+; RV64I-NEXT:    addiw a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -16
+; RV64I-NEXT:    addiw a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    sd s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add s0, sp, a0
 ; RV64I-NEXT:    srli a0, sp, 12
 ; RV64I-NEXT:    slli sp, a0, 12
 ; RV64I-NEXT:    lui a0, 2
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    sub sp, s0, a0
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -16
+; RV64I-NEXT:    addiw a0, a0, -16
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld s0, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    addi a0, a0, -8
+; RV64I-NEXT:    addiw a0, a0, -8
 ; RV64I-NEXT:    add a0, sp, a0
 ; RV64I-NEXT:    ld ra, 0(a0)
 ; RV64I-NEXT:    lui a0, 3
-; RV64I-NEXT:    mv a0, a0
 ; RV64I-NEXT:    add sp, sp, a0
 ; RV64I-NEXT:    ret
   %1 = alloca i8, align 4096