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| author | Zakk Chen <zakk.chen@sifive.com> | 2019-11-28 18:00:54 -0800 |
|---|---|---|
| committer | Hans Wennborg <hans@chromium.org> | 2020-01-27 19:07:09 +0100 |
| commit | 72882ca30d87bd7ea85d8099e8b9d2244749b71e (patch) | |
| tree | 08dc97948df36efcacf5742a1152fce2504eb57b /llvm/test/CodeGen/RISCV | |
| parent | 4d342b7d8e9bc6f40001011b51b5ad812535c4a6 (diff) | |
| download | bcm5719-llvm-72882ca30d87bd7ea85d8099e8b9d2244749b71e.tar.gz bcm5719-llvm-72882ca30d87bd7ea85d8099e8b9d2244749b71e.zip | |
[RISCV] Support ABI checking with per function target-features
1. if users don't specific -mattr, the default target-feature come
from IR attribute.
2. fixed bug and re-land this patch
Reviewers: lenary, asb
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70837
(cherry picked from commit 0cb274de397a193fb37c60653b336d48a3a4f1bd)
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll index 8ed465ae85f..613a983f926 100644 --- a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll +++ b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll @@ -2,12 +2,17 @@ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s +; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \ +; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s + +; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension -; RV32IF-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi) define float @foo(i32 %a) nounwind #0 { -; RV32IF-ILP32: # %bb.0: -; RV32IF-ILP32-NEXT: fcvt.s.w ft0, a0 +; RV32IF-ILP32: fcvt.s.w ft0, a0 +; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0 +; RV32IF-ILP32F: fcvt.s.w fa0, a0 +; RV32IF-ILP32F-NEXT: ret %conv = sitofp i32 %a to float ret float %conv } |
