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| author | Luís Marques <luismarques@lowrisc.org> | 2019-11-24 15:23:29 +0000 |
|---|---|---|
| committer | Luís Marques <luismarques@lowrisc.org> | 2019-11-26 15:22:55 +0000 |
| commit | 6fd4c42fa815952b29bee573068d60d13f7c9f37 (patch) | |
| tree | 81e22f97305c6bd803ee5ebbf46ebaa77808133d /llvm/test/CodeGen/RISCV | |
| parent | d7be3eab5c0e1598e919973ed68a200997a4734a (diff) | |
| download | bcm5719-llvm-6fd4c42fa815952b29bee573068d60d13f7c9f37.tar.gz bcm5719-llvm-6fd4c42fa815952b29bee573068d60d13f7c9f37.zip | |
[LegalizeTypes][RISCV] Soften FCOPYSIGN operand
Summary: Adds support for softening FCOPYSIGN operands.
Adds RISC-V tests that exercise the new softening code.
Reviewers: asb, lenary, efriedma
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70679
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/copysign-casts.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll index 45faa230614..acd64c20365 100644 --- a/llvm/test/CodeGen/RISCV/copysign-casts.ll +++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll @@ -3,6 +3,8 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \ +; RUN: -target-abi ilp32f < %s | FileCheck %s -check-prefix=RV32IF ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \ ; RUN: -target-abi ilp32d < %s | FileCheck %s -check-prefix=RV32IFD ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \ @@ -37,6 +39,16 @@ define double @fold_promote(double %a, float %b) nounwind { ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; +; RV32IF-LABEL: fold_promote: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.x.w a2, fa0 +; RV32IF-NEXT: lui a3, 524288 +; RV32IF-NEXT: and a2, a2, a3 +; RV32IF-NEXT: addi a3, a3, -1 +; RV32IF-NEXT: and a1, a1, a3 +; RV32IF-NEXT: or a1, a1, a2 +; RV32IF-NEXT: ret +; ; RV32IFD-LABEL: fold_promote: ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fcvt.d.s ft0, fa1 @@ -75,6 +87,12 @@ define float @fold_demote(float %a, double %b) nounwind { ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; +; RV32IF-LABEL: fold_demote: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.w.x ft0, a1 +; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0 +; RV32IF-NEXT: ret +; ; RV32IFD-LABEL: fold_demote: ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fcvt.s.d ft0, fa1 |
