[RISCV] Implement lowering of ISD::SELECT

Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch
will be created in the case where an ISD::SELECT condition value is created by
an ISD::SETCC node, which operates on XLen types. Other datatypes such as
floating point don't have conditional branch instructions, and lowering
ISD::SELECT allows more flexibility for handling these cases.

Differential Revision: https://reviews.llvm.org/D29937

llvm-svn: 318735

2 files changed, 118 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/bare-select.ll b/llvm/test/CodeGen/RISCV/bare-select.ll
new file mode 100644
index 00000000000..d4a29ffa29b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/bare-select.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+
+define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
+; RV32I-LABEL: bare_select:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    addi a3, zero, 0
+; RV32I-NEXT:    bne a0, a3, .LBB0_2
+; RV32I-NEXT:  # BB#1:
+; RV32I-NEXT:    addi a1, a2, 0
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    addi a0, a1, 0
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = select i1 %a, i32 %b, i32 %c
+  ret i32 %1
+}
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
new file mode 100644
index 00000000000..c1a570c5c98
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -0,0 +1,100 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
+define i32 @foo(i32 %a, i32 *%b) {
+; RV32I-LABEL: foo:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    beq a0, a2, .LBB0_2
+; RV32I-NEXT:  # BB#1:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bne a0, a2, .LBB0_4
+; RV32I-NEXT:  # BB#3:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_4:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bltu a2, a0, .LBB0_6
+; RV32I-NEXT:  # BB#5:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_6:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bgeu a0, a2, .LBB0_8
+; RV32I-NEXT:  # BB#7:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_8:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bltu a0, a2, .LBB0_10
+; RV32I-NEXT:  # BB#9:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_10:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bgeu a2, a0, .LBB0_12
+; RV32I-NEXT:  # BB#11:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_12:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    blt a2, a0, .LBB0_14
+; RV32I-NEXT:  # BB#13:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_14:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    bge a0, a2, .LBB0_16
+; RV32I-NEXT:  # BB#15:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_16:
+; RV32I-NEXT:    lw a2, 0(a1)
+; RV32I-NEXT:    blt a0, a2, .LBB0_18
+; RV32I-NEXT:  # BB#17:
+; RV32I-NEXT:    addi a0, a2, 0
+; RV32I-NEXT:  .LBB0_18:
+; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    bge a1, a0, .LBB0_20
+; RV32I-NEXT:  # BB#19:
+; RV32I-NEXT:    addi a0, a1, 0
+; RV32I-NEXT:  .LBB0_20:
+; RV32I-NEXT:    jalr zero, ra, 0
+  %val1 = load volatile i32, i32* %b
+  %tst1 = icmp eq i32 %a, %val1
+  %val2 = select i1 %tst1, i32 %a, i32 %val1
+
+  %val3 = load volatile i32, i32* %b
+  %tst2 = icmp ne i32 %val2, %val3
+  %val4 = select i1 %tst2, i32 %val2, i32 %val3
+
+  %val5 = load volatile i32, i32* %b
+  %tst3 = icmp ugt i32 %val4, %val5
+  %val6 = select i1 %tst3, i32 %val4, i32 %val5
+
+  %val7 = load volatile i32, i32* %b
+  %tst4 = icmp uge i32 %val6, %val7
+  %val8 = select i1 %tst4, i32 %val6, i32 %val7
+
+  %val9 = load volatile i32, i32* %b
+  %tst5 = icmp ult i32 %val8, %val9
+  %val10 = select i1 %tst5, i32 %val8, i32 %val9
+
+  %val11 = load volatile i32, i32* %b
+  %tst6 = icmp ule i32 %val10, %val11
+  %val12 = select i1 %tst6, i32 %val10, i32 %val11
+
+  %val13 = load volatile i32, i32* %b
+  %tst7 = icmp sgt i32 %val12, %val13
+  %val14 = select i1 %tst7, i32 %val12, i32 %val13
+
+  %val15 = load volatile i32, i32* %b
+  %tst8 = icmp sge i32 %val14, %val15
+  %val16 = select i1 %tst8, i32 %val14, i32 %val15
+
+  %val17 = load volatile i32, i32* %b
+  %tst9 = icmp slt i32 %val16, %val17
+  %val18 = select i1 %tst9, i32 %val16, i32 %val17
+
+  %val19 = load volatile i32, i32* %b
+  %tst10 = icmp sle i32 %val18, %val19
+  %val20 = select i1 %tst10, i32 %val18, i32 %val19
+
+  ret i32 %val20
+}