diff options
| author | Kamlesh Kumar <kamleshbhalui@gmail.com> | 2020-06-18 19:16:54 +0530 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-06-25 16:13:53 -0700 |
| commit | 249fef00d925ce56d7eb1f6910064a586716cba4 (patch) | |
| tree | a405cedd72a8e4a455fb956031e848fb65e62c44 /llvm/test/CodeGen/RISCV | |
| parent | 71c14cd5aee72a7502a45068ec73487d1f9e019c (diff) | |
| download | bcm5719-llvm-249fef00d925ce56d7eb1f6910064a586716cba4.tar.gz bcm5719-llvm-249fef00d925ce56d7eb1f6910064a586716cba4.zip | |
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
Since i32 is not legal in riscv64,
it always promoted to i64 before emitting lib call and
for conversions like float/double to int and float/double to unsigned int
wrong lib call was emitted. This commit fix it using custom lowering.
Differential Revision: https://reviews.llvm.org/D80526
(cherry picked from commit 7622ea5835f0381a426e504f4c03f11733732b83)
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll | 124 |
1 files changed, 122 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll index e486a48cb22..5888fc3157c 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll @@ -174,7 +174,7 @@ define i32 @fcvt_w_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) -; RV64I-NEXT: call __fixsfdi +; RV64I-NEXT: call __fixsfsi ; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -187,7 +187,7 @@ define i32 @fcvt_wu_s(float %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) -; RV64I-NEXT: call __fixunssfdi +; RV64I-NEXT: call __fixunssfsi ; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -710,3 +710,123 @@ define float @fp_trunc(double %a) nounwind { %conv = fptrunc double %a to float ret float %conv } + +define i32 @fp32_to_ui32(float %a) nounwind { +; RV64I-LABEL: fp32_to_ui32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixunssfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = fptoui float %a to i32 + ret i32 %conv +} + +define i32 @fp32_to_si32(float %a) nounwind { +; RV64I-LABEL: fp32_to_si32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixsfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = fptosi float %a to i32 + ret i32 %conv +} + +define i32 @fp64_to_ui32(double %a) nounwind { +; RV64I-LABEL: fp64_to_ui32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixunsdfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = fptoui double %a to i32 + ret i32 %conv +} + +define i32 @fp64_to_si32(double %a) nounwind { +; RV64I-LABEL: fp64_to_si32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixdfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = fptosi double %a to i32 + ret i32 %conv +} + + + +declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata) +declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata) +declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata) +declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata) + +define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp { +; RV64I-LABEL: strict_fp32_to_ui32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixunssfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") + ret i32 %conv +} + +define i32 @strict_fp32_to_si32(float %a) nounwind strictfp { +; RV64I-LABEL: strict_fp32_to_si32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixsfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") + ret i32 %conv +} + +define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp { +; RV64I-LABEL: strict_fp64_to_ui32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixunsdfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") + ret i32 %conv +} + +define i32 @struct_fp64_to_si32(double %a) nounwind strictfp { +; RV64I-LABEL: struct_fp64_to_si32: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) +; RV64I-NEXT: call __fixdfsi +; RV64I-NEXT: ld ra, 8(sp) +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") + ret i32 %conv +} + |
