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| author | Luis Marques <luismarques@lowrisc.org> | 2019-09-17 11:15:35 +0000 |
|---|---|---|
| committer | Luis Marques <luismarques@lowrisc.org> | 2019-09-17 11:15:35 +0000 |
| commit | 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec (patch) | |
| tree | e71d5a01eeebf585596a126cd834fddab0c2c784 /llvm/test/CodeGen/RISCV/float-arith.ll | |
| parent | 3ab9e8b81858cdcf4f381b4238315cb1d434e984 (diff) | |
| download | bcm5719-llvm-3d0fbafd0bce43bb9106230a45d1130f7a40e5ec.tar.gz bcm5719-llvm-3d0fbafd0bce43bb9106230a45d1130f7a40e5ec.zip | |
[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.
Differential Revision: https://reviews.llvm.org/D66973
llvm-svn: 372106
Diffstat (limited to 'llvm/test/CodeGen/RISCV/float-arith.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/float-arith.ll | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index a668b7e4942..5244a69a6fa 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -339,26 +339,26 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind { define float @fmsub_s(float %a, float %b, float %c) nounwind { ; RV32IF-LABEL: fmsub_s: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a2 -; RV32IF-NEXT: lui a2, %hi(.LCPI15_0) -; RV32IF-NEXT: addi a2, a2, %lo(.LCPI15_0) -; RV32IF-NEXT: flw ft1, 0(a2) -; RV32IF-NEXT: fadd.s ft0, ft0, ft1 +; RV32IF-NEXT: lui a3, %hi(.LCPI15_0) +; RV32IF-NEXT: addi a3, a3, %lo(.LCPI15_0) +; RV32IF-NEXT: flw ft0, 0(a3) ; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft2, a0 +; RV32IF-NEXT: fmv.w.x ft3, a2 +; RV32IF-NEXT: fadd.s ft0, ft3, ft0 ; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fmsub_s: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a2 -; RV64IF-NEXT: lui a2, %hi(.LCPI15_0) -; RV64IF-NEXT: addi a2, a2, %lo(.LCPI15_0) -; RV64IF-NEXT: flw ft1, 0(a2) -; RV64IF-NEXT: fadd.s ft0, ft0, ft1 +; RV64IF-NEXT: lui a3, %hi(.LCPI15_0) +; RV64IF-NEXT: addi a3, a3, %lo(.LCPI15_0) +; RV64IF-NEXT: flw ft0, 0(a3) ; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft2, a0 +; RV64IF-NEXT: fmv.w.x ft3, a2 +; RV64IF-NEXT: fadd.s ft0, ft3, ft0 ; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret @@ -371,29 +371,29 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind { define float @fnmadd_s(float %a, float %b, float %c) nounwind { ; RV32IF-LABEL: fnmadd_s: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a2 -; RV32IF-NEXT: lui a2, %hi(.LCPI16_0) -; RV32IF-NEXT: addi a2, a2, %lo(.LCPI16_0) -; RV32IF-NEXT: flw ft1, 0(a2) -; RV32IF-NEXT: fadd.s ft0, ft0, ft1 -; RV32IF-NEXT: fmv.w.x ft2, a0 -; RV32IF-NEXT: fadd.s ft1, ft2, ft1 -; RV32IF-NEXT: fmv.w.x ft2, a1 -; RV32IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0 +; RV32IF-NEXT: lui a3, %hi(.LCPI16_0) +; RV32IF-NEXT: addi a3, a3, %lo(.LCPI16_0) +; RV32IF-NEXT: flw ft0, 0(a3) +; RV32IF-NEXT: fmv.w.x ft1, a1 +; RV32IF-NEXT: fmv.w.x ft2, a2 +; RV32IF-NEXT: fmv.w.x ft3, a0 +; RV32IF-NEXT: fadd.s ft3, ft3, ft0 +; RV32IF-NEXT: fadd.s ft0, ft2, ft0 +; RV32IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fnmadd_s: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a2 -; RV64IF-NEXT: lui a2, %hi(.LCPI16_0) -; RV64IF-NEXT: addi a2, a2, %lo(.LCPI16_0) -; RV64IF-NEXT: flw ft1, 0(a2) -; RV64IF-NEXT: fadd.s ft0, ft0, ft1 -; RV64IF-NEXT: fmv.w.x ft2, a0 -; RV64IF-NEXT: fadd.s ft1, ft2, ft1 -; RV64IF-NEXT: fmv.w.x ft2, a1 -; RV64IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0 +; RV64IF-NEXT: lui a3, %hi(.LCPI16_0) +; RV64IF-NEXT: addi a3, a3, %lo(.LCPI16_0) +; RV64IF-NEXT: flw ft0, 0(a3) +; RV64IF-NEXT: fmv.w.x ft1, a1 +; RV64IF-NEXT: fmv.w.x ft2, a2 +; RV64IF-NEXT: fmv.w.x ft3, a0 +; RV64IF-NEXT: fadd.s ft3, ft3, ft0 +; RV64IF-NEXT: fadd.s ft0, ft2, ft0 +; RV64IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %a_ = fadd float 0.0, %a @@ -407,26 +407,26 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind { define float @fnmsub_s(float %a, float %b, float %c) nounwind { ; RV32IF-LABEL: fnmsub_s: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: lui a0, %hi(.LCPI17_0) -; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0) -; RV32IF-NEXT: flw ft1, 0(a0) -; RV32IF-NEXT: fadd.s ft0, ft0, ft1 +; RV32IF-NEXT: lui a3, %hi(.LCPI17_0) +; RV32IF-NEXT: addi a3, a3, %lo(.LCPI17_0) +; RV32IF-NEXT: flw ft0, 0(a3) ; RV32IF-NEXT: fmv.w.x ft1, a2 ; RV32IF-NEXT: fmv.w.x ft2, a1 +; RV32IF-NEXT: fmv.w.x ft3, a0 +; RV32IF-NEXT: fadd.s ft0, ft3, ft0 ; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fnmsub_s: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: lui a0, %hi(.LCPI17_0) -; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0) -; RV64IF-NEXT: flw ft1, 0(a0) -; RV64IF-NEXT: fadd.s ft0, ft0, ft1 +; RV64IF-NEXT: lui a3, %hi(.LCPI17_0) +; RV64IF-NEXT: addi a3, a3, %lo(.LCPI17_0) +; RV64IF-NEXT: flw ft0, 0(a3) ; RV64IF-NEXT: fmv.w.x ft1, a2 ; RV64IF-NEXT: fmv.w.x ft2, a1 +; RV64IF-NEXT: fmv.w.x ft3, a0 +; RV64IF-NEXT: fadd.s ft0, ft3, ft0 ; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret |
