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| author | Alex Bradbury <asb@lowrisc.org> | 2018-04-18 19:02:31 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-04-18 19:02:31 +0000 |
| commit | 099c720426b2e54fc17c8fddc270ea9a8ca2e356 (patch) | |
| tree | 452bb232a9c6b6ff04f3a0859da68c6ced2a6ecb /llvm/test/CodeGen/RISCV/float-arith.ll | |
| parent | 5832eb4cfd2fcb20fc9f25b9d9bdc2930df3cb27 (diff) | |
| download | bcm5719-llvm-099c720426b2e54fc17c8fddc270ea9a8ca2e356.tar.gz bcm5719-llvm-099c720426b2e54fc17c8fddc270ea9a8ca2e356.zip | |
Revert "[RISCV] implement li pseudo instruction"
Reverts rL330224, while issues with the C extension and missed common
subexpression elimination opportunities are addressed. Neither of these issues
are visible in current RISC-V backend unit tests, which clearly need
expanding.
llvm-svn: 330281
Diffstat (limited to 'llvm/test/CodeGen/RISCV/float-arith.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/float-arith.ll | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index f3ec61b4357..c7c5f91301e 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -84,6 +84,7 @@ define float @fneg_s(float %a) nounwind { ; RV32IF-LABEL: fneg_s: ; RV32IF: # %bb.0: ; RV32IF-NEXT: lui a1, 524288 +; RV32IF-NEXT: mv a1, a1 ; RV32IF-NEXT: xor a0, a0, a1 ; RV32IF-NEXT: ret %1 = fsub float -0.0, %a @@ -96,6 +97,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV32IF-LABEL: fsgnjn_s: ; RV32IF: # %bb.0: ; RV32IF-NEXT: lui a2, 524288 +; RV32IF-NEXT: mv a2, a2 ; RV32IF-NEXT: xor a1, a1, a2 ; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0 |
