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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-03 05:22:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-12-03 05:22:35 +0000 |
| commit | becd656c7caf68d443dc721ae01590d200beed9c (patch) | |
| tree | e2da004150f309650b5175f7cae74a41a00bfba0 /llvm/test/CodeGen/R600/setcc.ll | |
| parent | 2f470c62cba90ca47f3aead9b0344c4c183dd6be (diff) | |
| download | bcm5719-llvm-becd656c7caf68d443dc721ae01590d200beed9c.tar.gz bcm5719-llvm-becd656c7caf68d443dc721ae01590d200beed9c.zip | |
R600/SI: Remove i1 pseudo VALU ops
Select i1 logical ops directly to 64-bit SALU instructions.
Vector i1 values are always really in SGPRs, with each
bit for each item in the wave. This saves about 4 instructions
when and/or/xoring any condition, and also helps write conditions
that need to be passed in vcc.
This should work correctly now that the SGPR live range
fixing pass works. More work is needed to eliminate the VReg_1
pseudo regclass and possibly the entire SILowerI1Copies pass.
llvm-svn: 223206
Diffstat (limited to 'llvm/test/CodeGen/R600/setcc.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/setcc.ll | 42 |
1 files changed, 20 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/R600/setcc.ll b/llvm/test/CodeGen/R600/setcc.ll index 371ebbedf18..1cca2bc21e2 100644 --- a/llvm/test/CodeGen/R600/setcc.ll +++ b/llvm/test/CodeGen/R600/setcc.ll @@ -96,11 +96,12 @@ entry: ; R600-DAG: SETNE_DX10 ; R600-DAG: AND_INT ; R600-DAG: SETNE_INT -; SI: v_cmp_o_f32 -; SI: v_cmp_neq_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_and_b32_e32 + +; SI-DAG: v_cmp_o_f32_e32 vcc +; SI-DAG: v_cmp_neq_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] +; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc +; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[AND]] +; SI: buffer_store_dword [[VRESULT]] define void @f32_one(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp one float %a, %b @@ -130,11 +131,12 @@ entry: ; R600-DAG: SETE_DX10 ; R600-DAG: OR_INT ; R600-DAG: SETNE_INT -; SI: v_cmp_u_f32 -; SI: v_cmp_eq_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_or_b32_e32 + +; SI-DAG: v_cmp_u_f32_e32 vcc +; SI-DAG: v_cmp_eq_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]] +; SI: s_or_b64 [[OR:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc +; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[OR]] +; SI: buffer_store_dword [[VRESULT]] define void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ueq float %a, %b @@ -148,9 +150,8 @@ entry: ; R600: SETE_DX10 ; SI: v_cmp_u_f32 ; SI: v_cmp_gt_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_or_b32_e32 +; SI: s_or_b64 +; SI: v_cndmask_b32 define void @f32_ugt(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ugt float %a, %b @@ -164,9 +165,8 @@ entry: ; R600: SETE_DX10 ; SI: v_cmp_u_f32 ; SI: v_cmp_ge_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_or_b32_e32 +; SI: s_or_b64 +; SI: v_cndmask_b32 define void @f32_uge(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp uge float %a, %b @@ -180,9 +180,8 @@ entry: ; R600: SETE_DX10 ; SI: v_cmp_u_f32 ; SI: v_cmp_lt_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_or_b32_e32 +; SI: s_or_b64 +; SI: v_cndmask_b32 define void @f32_ult(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ult float %a, %b @@ -196,9 +195,8 @@ entry: ; R600: SETE_DX10 ; SI: v_cmp_u_f32 ; SI: v_cmp_le_f32 -; SI: v_cndmask_b32_e64 -; SI: v_cndmask_b32_e64 -; SI: v_or_b32_e32 +; SI: s_or_b64 +; SI: v_cndmask_b32 define void @f32_ule(i32 addrspace(1)* %out, float %a, float %b) { entry: %0 = fcmp ule float %a, %b |
