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| author | Sanjay Patel <spatel@rotateright.com> | 2017-06-27 23:15:01 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-06-27 23:15:01 +0000 |
| commit | 4b23fa0abf4a8397f5a4e89c1350bdbeb55abd01 (patch) | |
| tree | 8fe1efbdef2cca621f7ed8b823e8e93178cf3af1 /llvm/test/CodeGen/PowerPC | |
| parent | c5fa6358ba73e50f06348fb56132c3700aaa1b3e (diff) | |
| download | bcm5719-llvm-4b23fa0abf4a8397f5a4e89c1350bdbeb55abd01.tar.gz bcm5719-llvm-4b23fa0abf4a8397f5a4e89c1350bdbeb55abd01.zip | |
[CGP] add specialization for memcmp expansion with only one basic block
llvm-svn: 306485
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/memcmp.ll | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/memcmpIR.ll | 28 |
2 files changed, 18 insertions, 26 deletions
diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll index 039c48b2a96..7cec2a1331d 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp.ll @@ -13,11 +13,10 @@ entry: ; CHECK: ldbrx [[LOAD1:[0-9]+]] ; CHECK-NEXT: ldbrx [[LOAD2:[0-9]+]] ; CHECK-NEXT: li [[LI:[0-9]+]], 1 -; CHECK-NEXT: cmpld [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: li [[LI2:[0-9]+]], -1 +; CHECK-NEXT: cmpld [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0 ; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2 -; CHECK-NEXT: extsw 3, [[ISEL2]] ; CHECK-NEXT: blr } @@ -34,11 +33,10 @@ entry: ; CHECK: lwbrx [[LOAD1:[0-9]+]] ; CHECK-NEXT: lwbrx [[LOAD2:[0-9]+]] ; CHECK-NEXT: li [[LI:[0-9]+]], 1 -; CHECK-NEXT: cmpld [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: li [[LI2:[0-9]+]], -1 +; CHECK-NEXT: cmplw [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0 ; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2 -; CHECK-NEXT: extsw 3, [[ISEL2]] ; CHECK-NEXT: blr } @@ -55,11 +53,10 @@ entry: ; CHECK: lhbrx [[LOAD1:[0-9]+]] ; CHECK-NEXT: lhbrx [[LOAD2:[0-9]+]] ; CHECK-NEXT: li [[LI:[0-9]+]], 1 -; CHECK-NEXT: cmpld [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: li [[LI2:[0-9]+]], -1 +; CHECK-NEXT: cmplw [[LOAD1]], [[LOAD2]] ; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0 ; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2 -; CHECK-NEXT: extsw 3, [[ISEL2]] ; CHECK-NEXT: blr } @@ -75,8 +72,11 @@ entry: ; CHECK-LABEL: @test4 ; CHECK: lbz [[LOAD1:[0-9]+]] ; CHECK-NEXT: lbz [[LOAD2:[0-9]+]] -; CHECK-NEXT: subf [[SUB:[0-9]+]], [[LOAD2]], [[LOAD1]] -; CHECK-NEXT: extsw 3, [[SUB]] +; CHECK-NEXT: li [[LI:[0-9]+]], 1 +; CHECK-NEXT: li [[LI2:[0-9]+]], -1 +; CHECK-NEXT: cmplw [[LOAD1]], [[LOAD2]] +; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0 +; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2 ; CHECK-NEXT: blr } diff --git a/llvm/test/CodeGen/PowerPC/memcmpIR.ll b/llvm/test/CodeGen/PowerPC/memcmpIR.ll index 044c8d5aa33..55f48ad19a6 100644 --- a/llvm/test/CodeGen/PowerPC/memcmpIR.ll +++ b/llvm/test/CodeGen/PowerPC/memcmpIR.ll @@ -59,28 +59,20 @@ define signext i32 @test2(i32* nocapture readonly %buffer1, i32* nocapture reado ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32* ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]]) ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]]) - ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[BSWAP1]] to i64 - ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[BSWAP2]] to i64 - ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]] - ; CHECK-NEXT: br i1 [[ICMP]], label %endblock, label %res_block - - ; CHECK-LABEL: res_block:{{.*}} - ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64 - ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1 - ; CHECK-NEXT: br label %endblock + ; CHECK-NEXT: [[CMP1:%[0-9]+]] = icmp ne i32 [[BSWAP1]], [[BSWAP2]] + ; CHECK-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[BSWAP1]], [[BSWAP2]] + ; CHECK-NEXT: [[SELECT1:%[0-9]+]] = select i1 [[CMP2]], i32 -1, i32 1 + ; CHECK-NEXT: [[SELECT2:%[0-9]+]] = select i1 [[CMP1]], i32 [[SELECT1]], i32 0 + ; CHECK-NEXT: ret i32 [[SELECT2]] ; CHECK-BE-LABEL: @test2( ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, i32* ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32* - ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[LOAD1]] to i64 - ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[LOAD2]] to i64 - ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]] - ; CHECK-BE-NEXT: br i1 [[ICMP]], label %endblock, label %res_block - - ; CHECK-BE-LABEL: res_block:{{.*}} - ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64 - ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1 - ; CHECK-BE-NEXT: br label %endblock + ; CHECK-BE-NEXT: [[CMP1:%[0-9]+]] = icmp ne i32 [[LOAD1]], [[LOAD2]] + ; CHECK-BE-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[LOAD1]], [[LOAD2]] + ; CHECK-BE-NEXT: [[SELECT1:%[0-9]+]] = select i1 [[CMP2]], i32 -1, i32 1 + ; CHECK-BE-NEXT: [[SELECT2:%[0-9]+]] = select i1 [[CMP1]], i32 [[SELECT1]], i32 0 + ; CHECK-BE-NEXT: ret i32 [[SELECT2]] entry: %0 = bitcast i32* %buffer1 to i8* |

