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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-12-03 23:03:26 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-12-03 23:03:26 +0000
commit92fede361fa9881c518fadec89052a47567f4342 (patch)
treea439357f7a858f3459be8cb511e7cda96a221bcf /llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
parent66caac5735624f10a90921e43bb8c27eca58bee5 (diff)
downloadbcm5719-llvm-92fede361fa9881c518fadec89052a47567f4342.tar.gz
bcm5719-llvm-92fede361fa9881c518fadec89052a47567f4342.zip
DAG: Fold out out of bounds insert_vector_elt
getNode already prevents formation of out of bounds constant extract_vector_elts. Do the same for insert_vector_elt. llvm-svn: 288603
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll57
1 files changed, 32 insertions, 25 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
index 0dfba86420d..f42f7d11783 100644
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -3,6 +3,15 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind {
+ %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 1
+ %result = add <1 x i128> %x, %tmpvec
+ ret <1 x i128> %result
+; CHECK-LABEL: @out_of_bounds_insertelement
+; CHECK: # BB#0:
+; CHECK-NEXT: blr
+}
+
define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {
%result = add <1 x i128> %x, %y
ret <1 x i128> %result
@@ -19,8 +28,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
- %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
- %result = add <1 x i128> %x, %tmpvec2
+ %result = add <1 x i128> %x, %tmpvec
ret <1 x i128> %result
; CHECK-LABEL: @increment_by_val
; CHECK: vadduqm 2, 2, 3
@@ -42,32 +50,31 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
- %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
- %result = sub <1 x i128> %x, %tmpvec2
+ %result = sub <1 x i128> %x, %tmpvec
ret <1 x i128> %result
; CHECK-LABEL: @decrement_by_val
-; CHECK: vsubuqm 2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
}
-declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
+declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
<1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
+declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
<1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
<1 x i128> %y,
@@ -77,7 +84,7 @@ define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
; CHECK: vaddeuqm 2, 2, 3, 4
}
-define <1 x i128> @test_vaddcuq(<1 x i128> %x,
+define <1 x i128> @test_vaddcuq(<1 x i128> %x,
<1 x i128> %y) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
<1 x i128> %y)
@@ -86,8 +93,8 @@ define <1 x i128> @test_vaddcuq(<1 x i128> %x,
; CHECK: vaddcuq 2, 2, 3
}
-define <1 x i128> @test_vaddecuq(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vaddecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
<1 x i128> %y,
@@ -97,8 +104,8 @@ define <1 x i128> @test_vaddecuq(<1 x i128> %x,
; CHECK: vaddecuq 2, 2, 3, 4
}
-define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
<1 x i128> %y,
@@ -108,7 +115,7 @@ define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
; CHECK: vsubeuqm 2, 2, 3, 4
}
-define <1 x i128> @test_vsubcuq(<1 x i128> %x,
+define <1 x i128> @test_vsubcuq(<1 x i128> %x,
<1 x i128> %y) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
<1 x i128> %y)
@@ -117,8 +124,8 @@ define <1 x i128> @test_vsubcuq(<1 x i128> %x,
; CHECK: vsubcuq 2, 2, 3
}
-define <1 x i128> @test_vsubecuq(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vsubecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
<1 x i128> %y,
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