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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp7
-rw-r--r--llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll57
-rw-r--r--llvm/test/CodeGen/X86/avx512-insert-extract.ll6
3 files changed, 42 insertions, 28 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 71c83ae5c0f..fc0cdeebb63 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4145,6 +4145,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
break;
case ISD::VECTOR_SHUFFLE:
llvm_unreachable("should use getVectorShuffle constructor!");
+ case ISD::INSERT_VECTOR_ELT: {
+ ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3);
+ // INSERT_VECTOR_ELT into out-of-bounds element is an UNDEF
+ if (N3C && N3C->getZExtValue() >= N1.getValueType().getVectorNumElements())
+ return getUNDEF(VT);
+ break;
+ }
case ISD::INSERT_SUBVECTOR: {
SDValue Index = N3;
if (VT.isSimple() && N1.getValueType().isSimple()
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
index 0dfba86420d..f42f7d11783 100644
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -3,6 +3,15 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind {
+ %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 1
+ %result = add <1 x i128> %x, %tmpvec
+ ret <1 x i128> %result
+; CHECK-LABEL: @out_of_bounds_insertelement
+; CHECK: # BB#0:
+; CHECK-NEXT: blr
+}
+
define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {
%result = add <1 x i128> %x, %y
ret <1 x i128> %result
@@ -19,8 +28,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
- %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
- %result = add <1 x i128> %x, %tmpvec2
+ %result = add <1 x i128> %x, %tmpvec
ret <1 x i128> %result
; CHECK-LABEL: @increment_by_val
; CHECK: vadduqm 2, 2, 3
@@ -42,32 +50,31 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
- %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
- %result = sub <1 x i128> %x, %tmpvec2
+ %result = sub <1 x i128> %x, %tmpvec
ret <1 x i128> %result
; CHECK-LABEL: @decrement_by_val
-; CHECK: vsubuqm 2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
}
-declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
+declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
<1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
+declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
<1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
- <1 x i128> %y,
+declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind readnone
-define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
<1 x i128> %y,
@@ -77,7 +84,7 @@ define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
; CHECK: vaddeuqm 2, 2, 3, 4
}
-define <1 x i128> @test_vaddcuq(<1 x i128> %x,
+define <1 x i128> @test_vaddcuq(<1 x i128> %x,
<1 x i128> %y) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
<1 x i128> %y)
@@ -86,8 +93,8 @@ define <1 x i128> @test_vaddcuq(<1 x i128> %x,
; CHECK: vaddcuq 2, 2, 3
}
-define <1 x i128> @test_vaddecuq(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vaddecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
<1 x i128> %y,
@@ -97,8 +104,8 @@ define <1 x i128> @test_vaddecuq(<1 x i128> %x,
; CHECK: vaddecuq 2, 2, 3, 4
}
-define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
<1 x i128> %y,
@@ -108,7 +115,7 @@ define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
; CHECK: vsubeuqm 2, 2, 3, 4
}
-define <1 x i128> @test_vsubcuq(<1 x i128> %x,
+define <1 x i128> @test_vsubcuq(<1 x i128> %x,
<1 x i128> %y) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
<1 x i128> %y)
@@ -117,8 +124,8 @@ define <1 x i128> @test_vsubcuq(<1 x i128> %x,
; CHECK: vsubcuq 2, 2, 3
}
-define <1 x i128> @test_vsubecuq(<1 x i128> %x,
- <1 x i128> %y,
+define <1 x i128> @test_vsubecuq(<1 x i128> %x,
+ <1 x i128> %y,
<1 x i128> %z) nounwind {
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
<1 x i128> %y,
diff --git a/llvm/test/CodeGen/X86/avx512-insert-extract.ll b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
index b89cbce0592..c6cc7428997 100644
--- a/llvm/test/CodeGen/X86/avx512-insert-extract.ll
+++ b/llvm/test/CodeGen/X86/avx512-insert-extract.ll
@@ -727,18 +727,18 @@ define <4 x i64> @insert_v4i64(<4 x i64> %x, i64 %y , i64* %ptr) {
define <2 x i64> @insert_v2i64(<2 x i64> %x, i64 %y , i64* %ptr) {
; KNL-LABEL: insert_v2i64:
; KNL: ## BB#0:
+; KNL-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm0
; KNL-NEXT: vpinsrq $1, (%rsi), %xmm0, %xmm0
-; KNL-NEXT: vpinsrq $3, %rdi, %xmm0, %xmm0
; KNL-NEXT: retq
;
; SKX-LABEL: insert_v2i64:
; SKX: ## BB#0:
+; SKX-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm0
; SKX-NEXT: vpinsrq $1, (%rsi), %xmm0, %xmm0
-; SKX-NEXT: vpinsrq $3, %rdi, %xmm0, %xmm0
; SKX-NEXT: retq
%val = load i64, i64* %ptr
%r1 = insertelement <2 x i64> %x, i64 %val, i32 1
- %r2 = insertelement <2 x i64> %r1, i64 %y, i32 3
+ %r2 = insertelement <2 x i64> %r1, i64 %y, i32 0
ret <2 x i64> %r2
}
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