Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done

llvm-svn: 186280

30 files changed, 287 insertions, 287 deletions

diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index 6bc9ce2e764..54268cda84f 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -8,7 +8,7 @@ entry:
   %0 = atomicrmw add i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadAdd32:
+; CHECK-EL-LABEL:   AtomicLoadAdd32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -16,7 +16,7 @@ entry:
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicLoadAdd32:
+; CHECK-EB-LABEL:   AtomicLoadAdd32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -30,7 +30,7 @@ entry:
   %0 = atomicrmw nand i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadNand32:
+; CHECK-EL-LABEL:   AtomicLoadNand32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -39,7 +39,7 @@ entry:
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicLoadNand32:
+; CHECK-EB-LABEL:   AtomicLoadNand32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
@@ -57,14 +57,14 @@ entry:
   %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicSwap32:
+; CHECK-EL-LABEL:   AtomicSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 
-; CHECK-EB:   AtomicSwap32:
+; CHECK-EB-LABEL:   AtomicSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      ${{[0-9]+}}, 0($[[R0]])
@@ -80,7 +80,7 @@ entry:
   %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicCmpSwap32:
+; CHECK-EL-LABEL:   AtomicCmpSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $2, 0($[[R0]])
@@ -89,7 +89,7 @@ entry:
 ; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
 ; CHECK-EL:   $[[BB1]]:
 
-; CHECK-EB:   AtomicCmpSwap32:
+; CHECK-EB-LABEL:   AtomicCmpSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $2, 0($[[R0]])
@@ -108,7 +108,7 @@ entry:
   %0 = atomicrmw add i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadAdd8:
+; CHECK-EL-LABEL:   AtomicLoadAdd8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -133,7 +133,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadAdd8:
+; CHECK-EB-LABEL:   AtomicLoadAdd8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -165,7 +165,7 @@ entry:
   %0 = atomicrmw sub i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadSub8:
+; CHECK-EL-LABEL:   AtomicLoadSub8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -190,7 +190,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadSub8:
+; CHECK-EB-LABEL:   AtomicLoadSub8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -222,7 +222,7 @@ entry:
   %0 = atomicrmw nand i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadNand8:
+; CHECK-EL-LABEL:   AtomicLoadNand8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -248,7 +248,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadNand8:
+; CHECK-EB-LABEL:   AtomicLoadNand8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -281,7 +281,7 @@ entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicSwap8:
+; CHECK-EL-LABEL:   AtomicSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -305,7 +305,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicSwap8:
+; CHECK-EB-LABEL:   AtomicSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -336,7 +336,7 @@ entry:
   %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicCmpSwap8:
+; CHECK-EL-LABEL:   AtomicCmpSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -365,7 +365,7 @@ entry:
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicCmpSwap8:
+; CHECK-EB-LABEL:   AtomicCmpSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -403,14 +403,14 @@ entry:
   %0 = atomicrmw add i32* @countsint, i32 %v seq_cst
   ret i32 %0 
 
-; CHECK-EL:   CheckSync:
+; CHECK-EL-LABEL:   CheckSync:
 ; CHECK-EL:   sync 0
 ; CHECK-EL:   ll
 ; CHECK-EL:   sc
 ; CHECK-EL:   beq
 ; CHECK-EL:   sync 0
 
-; CHECK-EB:   CheckSync:
+; CHECK-EB-LABEL:   CheckSync:
 ; CHECK-EB:   sync 0
 ; CHECK-EB:   ll
 ; CHECK-EB:   sc
diff --git a/llvm/test/CodeGen/Mips/atomicops.ll b/llvm/test/CodeGen/Mips/atomicops.ll
index b9c3804e0d7..0f0f01afc14 100644
--- a/llvm/test/CodeGen/Mips/atomicops.ll
+++ b/llvm/test/CodeGen/Mips/atomicops.ll
@@ -7,7 +7,7 @@ entry:
   %0 = atomicrmw add i32* %mem, i32 %val seq_cst
   %add = add nsw i32 %0, %c
   ret i32 %add
-; 16: foo:
+; 16-LABEL: foo:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 }
@@ -26,7 +26,7 @@ entry:
   %4 = atomicrmw xchg i32* %x, i32 1 seq_cst
   %5 = load volatile i32* %x, align 4
   %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
-; 16: main:
+; 16-LABEL: main:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/biggot.ll b/llvm/test/CodeGen/Mips/biggot.ll
index c4ad851c825..da287eea6fd 100644
--- a/llvm/test/CodeGen/Mips/biggot.ll
+++ b/llvm/test/CodeGen/Mips/biggot.ll
@@ -31,12 +31,12 @@ declare void @foo0(i32)
 
 define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
 entry:
-; O32: foo2:
+; O32-LABEL: foo2:
 ; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; O32: addu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
 
-; N64: foo2:
+; N64-LABEL: foo2:
 ; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; N64: ld  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
diff --git a/llvm/test/CodeGen/Mips/brdelayslot.ll b/llvm/test/CodeGen/Mips/brdelayslot.ll
index d076f74e56d..82e4730b000 100644
--- a/llvm/test/CodeGen/Mips/brdelayslot.ll
+++ b/llvm/test/CodeGen/Mips/brdelayslot.ll
@@ -31,7 +31,7 @@ declare void @foo2(i32)
 ;
 define void @foo3(i32 %a) nounwind {
 entry:
-; Default:     foo3:
+; Default-LABEL:     foo3:
 ; Default:     jalr
 ; Default:     cvt.d.w
 
@@ -49,7 +49,7 @@ declare void @foo4(double)
 ; Check that branch delay slot can be filled with an instruction with operand
 ; $1.
 ;
-; Default:     foo5:
+; Default-LABEL:     foo5:
 ; Default-NOT: nop
 
 define void @foo5(i32 %a) nounwind {
@@ -76,7 +76,7 @@ if.end:
 
 ; Check that delay slot filler can place mov.s or mov.d in delay slot.
 ;
-; Default:     foo6:
+; Default-LABEL:     foo6:
 ; Default-NOT: nop
 ; Default:     .end foo6
 
@@ -90,7 +90,7 @@ declare void @foo7(double, float)
 
 ; Check that a store can move past other memory instructions.
 ;
-; STATICO1:      foo8:
+; STATICO1-LABEL:      foo8:
 ; STATICO1:      jalr ${{[0-9]+}}
 ; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
 
@@ -109,7 +109,7 @@ entry:
 ; Test searchForward. Check that the second jal's slot is filled with another
 ; instruction in the same block.
 ;
-; FORWARD:     foo10:
+; FORWARD-LABEL:     foo10:
 ; FORWARD:     jal foo11
 ; FORWARD:     jal foo11
 ; FORWARD-NOT: nop
@@ -130,7 +130,7 @@ declare void @foo11()
 ; Check that delay slots of branches in both the entry block and loop body are
 ; filled.
 ;
-; SUCCBB:      succbbs_loop1:
+; SUCCBB-LABEL:      succbbs_loop1:
 ; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
 ; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
@@ -158,7 +158,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 ; Check that the first branch has its slot filled.
 ;
-; SUCCBB:      succbbs_br1:
+; SUCCBB-LABEL:      succbbs_br1:
 ; SUCCBB:      beq ${{[0-9]+}}, $zero, $BB
 ; SUCCBB-NEXT: lw $25, %call16(foo100)
 
diff --git a/llvm/test/CodeGen/Mips/bswap.ll b/llvm/test/CodeGen/Mips/bswap.ll
index a8fc2cdc743..0da2d2b7c28 100644
--- a/llvm/test/CodeGen/Mips/bswap.ll
+++ b/llvm/test/CodeGen/Mips/bswap.ll
@@ -3,7 +3,7 @@
 
 define i32 @bswap32(i32 %x) nounwind readnone {
 entry:
-; MIPS32: bswap32:
+; MIPS32-LABEL: bswap32:
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
   %or.3 = call i32 @llvm.bswap.i32(i32 %x)
@@ -12,7 +12,7 @@ entry:
 
 define i64 @bswap64(i64 %x) nounwind readnone {
 entry:
-; MIPS64: bswap64:
+; MIPS64-LABEL: bswap64:
 ; MIPS64: dsbh $[[R0:[0-9]+]]
 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
   %or.7 = call i64 @llvm.bswap.i64(i64 %x)
diff --git a/llvm/test/CodeGen/Mips/check-noat.ll b/llvm/test/CodeGen/Mips/check-noat.ll
index bfeff677b34..cfcd367e87a 100644
--- a/llvm/test/CodeGen/Mips/check-noat.ll
+++ b/llvm/test/CodeGen/Mips/check-noat.ll
@@ -2,7 +2,7 @@
 
 define void @f() nounwind readnone {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: .set  noat
 ; CHECK: .set  at
 
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index a96929789b7..c24c5ac26ae 100644
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -22,11 +22,11 @@ entry:
 @c = global i32 1, align 4
 @d = global i32 0, align 4
 
-; O32: cmov2:
+; O32-LABEL: cmov2:
 ; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
 ; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
 ; O32: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
-; N64: cmov2:
+; N64-LABEL: cmov2:
 ; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
 ; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; N64: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
@@ -39,7 +39,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: cmov3:
+; O32-LABEL: cmov3:
 ; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
@@ -49,7 +49,7 @@ entry:
   ret i32 %cond
 }
 
-; N64: cmov4:
+; N64-LABEL: cmov4:
 ; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
@@ -67,7 +67,7 @@ entry:
 ;  (movz t, (setlt a, N + 1), f)
 ; if N + 1 fits in 16-bit.
 
-; O32: slti0:
+; O32-LABEL: slti0:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -78,7 +78,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti1:
+; O32-LABEL: slti1:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti1(i32 %a) {
@@ -88,7 +88,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti2:
+; O32-LABEL: slti2:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -99,7 +99,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti3:
+; O32-LABEL: slti3:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti3(i32 %a) {
@@ -111,7 +111,7 @@ entry:
 
 ; 64-bit patterns.
 
-; N64: slti64_0:
+; N64-LABEL: slti64_0:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -122,7 +122,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_1:
+; N64-LABEL: slti64_1:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_1(i64 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_2:
+; N64-LABEL: slti64_2:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -143,7 +143,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_3:
+; N64-LABEL: slti64_3:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_3(i64 %a) {
@@ -155,7 +155,7 @@ entry:
 
 ; sltiu instructions.
 
-; O32: sltiu0:
+; O32-LABEL: sltiu0:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -166,7 +166,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu1:
+; O32-LABEL: sltiu1:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu1(i32 %a) {
@@ -176,7 +176,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu2:
+; O32-LABEL: sltiu2:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -187,7 +187,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu3:
+; O32-LABEL: sltiu3:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu3(i32 %a) {
diff --git a/llvm/test/CodeGen/Mips/const-mult.ll b/llvm/test/CodeGen/Mips/const-mult.ll
index 291846440a7..8c0cbe3396b 100644
--- a/llvm/test/CodeGen/Mips/const-mult.ll
+++ b/llvm/test/CodeGen/Mips/const-mult.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
 
-; CHECK: mul5_32:
+; CHECK-LABEL: mul5_32:
 ; CHECK: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
 
@@ -12,7 +12,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     mul27_32:
+; CHECK-LABEL:     mul27_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
@@ -24,7 +24,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK:     muln2147483643_32:
+; CHECK-LABEL:     muln2147483643_32:
 ; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
 ; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
@@ -36,7 +36,7 @@ entry:
   ret i32 %mul
 }
 
-; CHECK64:     muln9223372036854775805_64:
+; CHECK64-LABEL:     muln9223372036854775805_64:
 ; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
 ; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
 ; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll
index 47cebbe4e52..a983c46766e 100644
--- a/llvm/test/CodeGen/Mips/divrem.ll
+++ b/llvm/test/CodeGen/Mips/divrem.ll
@@ -2,12 +2,12 @@
 ; RUN: llc -march=mips -mno-check-zero-division < %s |\
 ; RUN: FileCheck %s -check-prefix=NOCHECK
 
-; TRAP: sdiv1:
+; TRAP-LABEL: sdiv1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
 
-; NOCHECK: sdiv1:
+; NOCHECK-LABEL: sdiv1:
 ; NOCHECK-NOT: teq
 ; NOCHECK: .end sdiv1
 
@@ -17,7 +17,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: srem1:
+; TRAP-LABEL: srem1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
@@ -28,7 +28,7 @@ entry:
   ret i32 %rem
 }
 
-; TRAP: udiv1:
+; TRAP-LABEL: udiv1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
@@ -39,7 +39,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: urem1:
+; TRAP-LABEL: urem1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
index 9f2f0661f99..a5fe34c1f68 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
 
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -17,7 +17,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -34,7 +34,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -51,7 +51,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -68,7 +68,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -85,7 +85,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -102,7 +102,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -119,7 +119,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -136,7 +136,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -153,7 +153,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -170,7 +170,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -187,7 +187,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -204,7 +204,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -221,7 +221,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -238,7 +238,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -255,7 +255,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -272,7 +272,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -289,7 +289,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -306,7 +306,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -323,7 +323,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -340,7 +340,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -355,7 +355,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -370,7 +370,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -385,7 +385,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -400,7 +400,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -415,7 +415,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -430,7 +430,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -445,7 +445,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -460,7 +460,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -475,7 +475,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -490,7 +490,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -505,7 +505,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -520,7 +520,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -535,7 +535,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -550,7 +550,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -565,7 +565,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -580,7 +580,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -595,7 +595,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -610,7 +610,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -625,7 +625,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns.ll b/llvm/test/CodeGen/Mips/dsp-patterns.ll
index ae0167b015a..f5bb3abed90 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns.ll
@@ -128,7 +128,7 @@ entry:
   ret i64 %add
 }
 
-; R1: shift1_v2i16_shl_:
+; R1-LABEL: shift1_v2i16_shl_:
 ; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
@@ -140,7 +140,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2i16_sra_:
+; R1-LABEL: shift1_v2i16_sra_:
 ; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
@@ -152,9 +152,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2ui16_srl_:
+; R1-LABEL: shift1_v2ui16_srl_:
 ; R1-NOT: shrl.ph
-; R2: shift1_v2ui16_srl_:
+; R2-LABEL: shift1_v2ui16_srl_:
 ; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
@@ -166,7 +166,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_shl_:
+; R1-LABEL: shift1_v4i8_shl_:
 ; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
@@ -178,9 +178,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_sra_:
+; R1-LABEL: shift1_v4i8_sra_:
 ; R1-NOT: shra.qb
-; R2: shift1_v4i8_sra_:
+; R2-LABEL: shift1_v4i8_sra_:
 ; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
@@ -192,7 +192,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4ui8_srl_:
+; R1-LABEL: shift1_v4ui8_srl_:
 ; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll
index 74bdb6c082e..9f074d1ff9e 100644
--- a/llvm/test/CodeGen/Mips/ex2.ll
+++ b/llvm/test/CodeGen/Mips/ex2.ll
@@ -4,7 +4,7 @@
 @_ZTIPKc = external constant i8*
 
 define i32 @main() {
-; 16: main:
+; 16-LABEL: main:
 ; 16: 	.cfi_startproc
 ; 16: 	save	$ra, $s0, $s1, 32
 ; 16:   .cfi_def_cfa_offset 32
diff --git a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
index 01978994b2f..7bb4adc31bd 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -10,7 +10,7 @@
 ; X with -3
 define i32 @constraint_X() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_X:
+;CHECK_LITTLE_32-LABEL:   constraint_X:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -21,7 +21,7 @@ entry:
 ; x with -3
 define i32 @constraint_x() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_x:
+;CHECK_LITTLE_32-LABEL:   constraint_x:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -32,7 +32,7 @@ entry:
 ; d with -3
 define i32 @constraint_d() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_d:
+;CHECK_LITTLE_32-LABEL:   constraint_d:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:   #NO_APP
@@ -43,7 +43,7 @@ entry:
 ; m with -3
 define i32 @constraint_m() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_m:
+;CHECK_LITTLE_32-LABEL:   constraint_m:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-4
 ;CHECK_LITTLE_32:   #NO_APP
@@ -54,7 +54,7 @@ entry:
 ; z with -3
 define i32 @constraint_z() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_z:
+;CHECK_LITTLE_32-LABEL: constraint_z:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -71,7 +71,7 @@ entry:
 ; a long long in 32 bit mode (use to assert)
 define i32 @constraint_longlong() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_longlong:
+;CHECK_LITTLE_32-LABEL: constraint_longlong:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -82,7 +82,7 @@ entry:
 ; D, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_D() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_D:
+;CHECK_LITTLE_32-LABEL: constraint_D:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -91,7 +91,7 @@ entry:
 ;CHECK_LITTLE_32:    #NO_APP
 
 ; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32:    constraint_D:
+;CHECK_BIG_32-LABEL:    constraint_D:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -107,7 +107,7 @@ entry:
 ; L, in little endian the source reg will be 0 bytes into the long long
 define i32 @constraint_L() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_L:
+;CHECK_LITTLE_32-LABEL: constraint_L:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -115,7 +115,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32: constraint_L:
+;CHECK_BIG_32-LABEL: constraint_L:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -131,7 +131,7 @@ entry:
 ; M, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_M() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_M:
+;CHECK_LITTLE_32-LABEL: constraint_M:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -139,7 +139,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32:    constraint_M:
+;CHECK_BIG_32-LABEL:    constraint_M:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/largefr1.ll b/llvm/test/CodeGen/Mips/largefr1.ll
index 0fe89f71d9f..6c417d8bd26 100644
--- a/llvm/test/CodeGen/Mips/largefr1.ll
+++ b/llvm/test/CodeGen/Mips/largefr1.ll
@@ -22,7 +22,7 @@ entry:
 
 define i32 @main() nounwind {
 entry:
-; 1: main: 
+; 1-LABEL: main:
 ; 1: 1: 	.word	-797992
 ; 1:            li ${{[0-9]+}}, 12
 ; 1:            sll ${{[0-9]+}}, ${{[0-9]+}}, 16
diff --git a/llvm/test/CodeGen/Mips/mips16fpe.ll b/llvm/test/CodeGen/Mips/mips16fpe.ll
index 43354360796..10c5163f7fd 100644
--- a/llvm/test/CodeGen/Mips/mips16fpe.ll
+++ b/llvm/test/CodeGen/Mips/mips16fpe.ll
@@ -41,7 +41,7 @@
 
 define void @test_addsf3() nounwind {
 entry:
-;16hf: test_addsf3:
+;16hf-LABEL: test_addsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %add = fadd float %0, %1
@@ -52,7 +52,7 @@ entry:
 
 define void @test_adddf3() nounwind {
 entry:
-;16hf: test_adddf3:
+;16hf-LABEL: test_adddf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %add = fadd double %0, %1
@@ -63,7 +63,7 @@ entry:
 
 define void @test_subsf3() nounwind {
 entry:
-;16hf: test_subsf3:
+;16hf-LABEL: test_subsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %sub = fsub float %0, %1
@@ -74,7 +74,7 @@ entry:
 
 define void @test_subdf3() nounwind {
 entry:
-;16hf: test_subdf3:
+;16hf-LABEL: test_subdf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %sub = fsub double %0, %1
@@ -85,7 +85,7 @@ entry:
 
 define void @test_mulsf3() nounwind {
 entry:
-;16hf: test_mulsf3:
+;16hf-LABEL: test_mulsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %mul = fmul float %0, %1
@@ -96,7 +96,7 @@ entry:
 
 define void @test_muldf3() nounwind {
 entry:
-;16hf: test_muldf3:
+;16hf-LABEL: test_muldf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %mul = fmul double %0, %1
@@ -107,7 +107,7 @@ entry:
 
 define void @test_divsf3() nounwind {
 entry:
-;16hf: test_divsf3:
+;16hf-LABEL: test_divsf3:
   %0 = load float* @y, align 4
   %1 = load float* @x, align 4
   %div = fdiv float %0, %1
@@ -118,7 +118,7 @@ entry:
 
 define void @test_divdf3() nounwind {
 entry:
-;16hf: test_divdf3:
+;16hf-LABEL: test_divdf3:
   %0 = load double* @yd, align 8
   %mul = fmul double %0, 2.000000e+00
   %1 = load double* @xd, align 8
@@ -130,7 +130,7 @@ entry:
 
 define void @test_extendsfdf2() nounwind {
 entry:
-;16hf: test_extendsfdf2:
+;16hf-LABEL: test_extendsfdf2:
   %0 = load float* @x, align 4
   %conv = fpext float %0 to double
   store double %conv, double* @extendsfdf2_result, align 8
@@ -140,7 +140,7 @@ entry:
 
 define void @test_truncdfsf2() nounwind {
 entry:
-;16hf: test_truncdfsf2:
+;16hf-LABEL: test_truncdfsf2:
   %0 = load double* @xd2, align 8
   %conv = fptrunc double %0 to float
   store float %conv, float* @truncdfsf2_result, align 4
@@ -150,7 +150,7 @@ entry:
 
 define void @test_fix_truncsfsi() nounwind {
 entry:
-;16hf: test_fix_truncsfsi:
+;16hf-LABEL: test_fix_truncsfsi:
   %0 = load float* @x, align 4
   %conv = fptosi float %0 to i32
   store i32 %conv, i32* @fix_truncsfsi_result, align 4
@@ -160,7 +160,7 @@ entry:
 
 define void @test_fix_truncdfsi() nounwind {
 entry:
-;16hf: test_fix_truncdfsi:
+;16hf-LABEL: test_fix_truncdfsi:
   %0 = load double* @xd, align 8
   %conv = fptosi double %0 to i32
   store i32 %conv, i32* @fix_truncdfsi_result, align 4
@@ -170,7 +170,7 @@ entry:
 
 define void @test_floatsisf() nounwind {
 entry:
-;16hf: test_floatsisf:
+;16hf-LABEL: test_floatsisf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to float
   store float %conv, float* @floatsisf_result, align 4
@@ -180,7 +180,7 @@ entry:
 
 define void @test_floatsidf() nounwind {
 entry:
-;16hf: test_floatsidf:
+;16hf-LABEL: test_floatsidf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to double
   store double %conv, double* @floatsidf_result, align 8
@@ -190,7 +190,7 @@ entry:
 
 define void @test_floatunsisf() nounwind {
 entry:
-;16hf: test_floatunsisf:
+;16hf-LABEL: test_floatunsisf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to float
   store float %conv, float* @floatunsisf_result, align 4
@@ -200,7 +200,7 @@ entry:
 
 define void @test_floatunsidf() nounwind {
 entry:
-;16hf: test_floatunsidf:
+;16hf-LABEL: test_floatunsidf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to double
   store double %conv, double* @floatunsidf_result, align 8
@@ -210,7 +210,7 @@ entry:
 
 define void @test_eqsf2() nounwind {
 entry:
-;16hf: test_eqsf2:
+;16hf-LABEL: test_eqsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oeq float %0, %1
@@ -222,7 +222,7 @@ entry:
 
 define void @test_eqdf2() nounwind {
 entry:
-;16hf: test_eqdf2:
+;16hf-LABEL: test_eqdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oeq double %0, %1
@@ -234,7 +234,7 @@ entry:
 
 define void @test_nesf2() nounwind {
 entry:
-;16hf: test_nesf2:
+;16hf-LABEL: test_nesf2:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %cmp = fcmp une float %0, %1
@@ -246,7 +246,7 @@ entry:
 
 define void @test_nedf2() nounwind {
 entry:
-;16hf: test_nedf2:
+;16hf-LABEL: test_nedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %cmp = fcmp une double %0, %1
@@ -258,7 +258,7 @@ entry:
 
 define void @test_gesf2() nounwind {
 entry:
-;16hf: test_gesf2:
+;16hf-LABEL: test_gesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oge float %0, %1
@@ -273,7 +273,7 @@ entry:
 
 define void @test_gedf2() nounwind {
 entry:
-;16hf: test_gedf2:
+;16hf-LABEL: test_gedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oge double %0, %1
@@ -288,7 +288,7 @@ entry:
 
 define void @test_ltsf2() nounwind {
 entry:
-;16hf: test_ltsf2:
+;16hf-LABEL: test_ltsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp uge float %0, %1
@@ -304,7 +304,7 @@ entry:
 
 define void @test_ltdf2() nounwind {
 entry:
-;16hf: test_ltdf2:
+;16hf-LABEL: test_ltdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp uge double %0, %1
@@ -320,7 +320,7 @@ entry:
 
 define void @test_lesf2() nounwind {
 entry:
-;16hf: test_lesf2:
+;16hf-LABEL: test_lesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp ole float %0, %1
@@ -335,7 +335,7 @@ entry:
 
 define void @test_ledf2() nounwind {
 entry:
-;16hf: test_ledf2:
+;16hf-LABEL: test_ledf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp ole double %0, %1
@@ -350,7 +350,7 @@ entry:
 
 define void @test_gtsf2() nounwind {
 entry:
-;16hf: test_gtsf2:
+;16hf-LABEL: test_gtsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp ule float %0, %1
@@ -365,7 +365,7 @@ entry:
 
 define void @test_gtdf2() nounwind {
 entry:
-;16hf: test_gtdf2:
+;16hf-LABEL: test_gtdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp ule double %0, %1
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index ab0a3d6b50f..dc8bbfdd5ba 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -7,7 +7,7 @@
 @gf1 = external global float
 @gd1 = external global double
 
-; CHECK: addLD:
+; CHECK-LABEL: addLD:
 ; CHECK: ld $25, %call16(__addtf3)
 
 define fp128 @addLD() {
@@ -18,7 +18,7 @@ entry:
   ret fp128 %add
 }
 
-; CHECK: subLD:
+; CHECK-LABEL: subLD:
 ; CHECK: ld $25, %call16(__subtf3)
 
 define fp128 @subLD() {
@@ -29,7 +29,7 @@ entry:
   ret fp128 %sub
 }
 
-; CHECK: mulLD:
+; CHECK-LABEL: mulLD:
 ; CHECK: ld $25, %call16(__multf3)
 
 define fp128 @mulLD() {
@@ -40,7 +40,7 @@ entry:
   ret fp128 %mul
 }
 
-; CHECK: divLD:
+; CHECK-LABEL: divLD:
 ; CHECK: ld $25, %call16(__divtf3)
 
 define fp128 @divLD() {
@@ -51,7 +51,7 @@ entry:
   ret fp128 %div
 }
 
-; CHECK: conv_LD_char:
+; CHECK-LABEL: conv_LD_char:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_char(i8 signext %a) {
@@ -60,7 +60,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_short:
+; CHECK-LABEL: conv_LD_short:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_short(i16 signext %a) {
@@ -69,7 +69,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_int:
+; CHECK-LABEL: conv_LD_int:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_int(i32 %a) {
@@ -78,7 +78,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_LL:
+; CHECK-LABEL: conv_LD_LL:
 ; CHECK: ld $25, %call16(__floatditf)
 
 define fp128 @conv_LD_LL(i64 %a) {
@@ -87,7 +87,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UChar:
+; CHECK-LABEL: conv_LD_UChar:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UChar(i8 zeroext %a) {
@@ -96,7 +96,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UShort:
+; CHECK-LABEL: conv_LD_UShort:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UShort(i16 zeroext %a) {
@@ -105,7 +105,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UInt:
+; CHECK-LABEL: conv_LD_UInt:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UInt(i32 %a) {
@@ -114,7 +114,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_ULL:
+; CHECK-LABEL: conv_LD_ULL:
 ; CHECK: ld $25, %call16(__floatunditf)
 
 define fp128 @conv_LD_ULL(i64 %a) {
@@ -123,7 +123,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_char_LD:
+; CHECK-LABEL: conv_char_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i8 @conv_char_LD(fp128 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_short_LD:
+; CHECK-LABEL: conv_short_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i16 @conv_short_LD(fp128 %a) {
@@ -141,7 +141,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_int_LD:
+; CHECK-LABEL: conv_int_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define i32 @conv_int_LD(fp128 %a) {
@@ -150,7 +150,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_LL_LD:
+; CHECK-LABEL: conv_LL_LD:
 ; CHECK: ld $25, %call16(__fixtfdi)
 
 define i64 @conv_LL_LD(fp128 %a) {
@@ -159,7 +159,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_UChar_LD:
+; CHECK-LABEL: conv_UChar_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i8 @conv_UChar_LD(fp128 %a) {
@@ -168,7 +168,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_UShort_LD:
+; CHECK-LABEL: conv_UShort_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i16 @conv_UShort_LD(fp128 %a) {
@@ -177,7 +177,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_UInt_LD:
+; CHECK-LABEL: conv_UInt_LD:
 ; CHECK: ld $25, %call16(__fixunstfsi)
 
 define i32 @conv_UInt_LD(fp128 %a) {
@@ -186,7 +186,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_ULL_LD:
+; CHECK-LABEL: conv_ULL_LD:
 ; CHECK: ld $25, %call16(__fixunstfdi)
 
 define i64 @conv_ULL_LD(fp128 %a) {
@@ -195,7 +195,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_LD_float:
+; CHECK-LABEL: conv_LD_float:
 ; CHECK: ld $25, %call16(__extendsftf2)
 
 define fp128 @conv_LD_float(float %a) {
@@ -204,7 +204,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_double:
+; CHECK-LABEL: conv_LD_double:
 ; CHECK: ld $25, %call16(__extenddftf2)
 
 define fp128 @conv_LD_double(double %a) {
@@ -213,7 +213,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_float_LD:
+; CHECK-LABEL: conv_float_LD:
 ; CHECK: ld $25, %call16(__trunctfsf2)
 
 define float @conv_float_LD(fp128 %a) {
@@ -222,7 +222,7 @@ entry:
   ret float %conv
 }
 
-; CHECK: conv_double_LD:
+; CHECK-LABEL: conv_double_LD:
 ; CHECK: ld $25, %call16(__trunctfdf2)
 
 define double @conv_double_LD(fp128 %a) {
@@ -231,7 +231,7 @@ entry:
   ret double %conv
 }
 
-; CHECK:             libcall1_fabsl:
+; CHECK-LABEL:             libcall1_fabsl:
 ; CHECK-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
 ; CHECK-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
 ; CHECK-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
@@ -248,7 +248,7 @@ entry:
 
 declare fp128 @fabsl(fp128) #1
 
-; CHECK: libcall1_ceill:
+; CHECK-LABEL: libcall1_ceill:
 ; CHECK: ld $25, %call16(ceill)
 
 define fp128 @libcall1_ceill() {
@@ -260,7 +260,7 @@ entry:
 
 declare fp128 @ceill(fp128) #1
 
-; CHECK: libcall1_sinl:
+; CHECK-LABEL: libcall1_sinl:
 ; CHECK: ld $25, %call16(sinl)
 
 define fp128 @libcall1_sinl() {
@@ -272,7 +272,7 @@ entry:
 
 declare fp128 @sinl(fp128) #2
 
-; CHECK: libcall1_cosl:
+; CHECK-LABEL: libcall1_cosl:
 ; CHECK: ld $25, %call16(cosl)
 
 define fp128 @libcall1_cosl() {
@@ -284,7 +284,7 @@ entry:
 
 declare fp128 @cosl(fp128) #2
 
-; CHECK: libcall1_expl:
+; CHECK-LABEL: libcall1_expl:
 ; CHECK: ld $25, %call16(expl)
 
 define fp128 @libcall1_expl() {
@@ -296,7 +296,7 @@ entry:
 
 declare fp128 @expl(fp128) #2
 
-; CHECK: libcall1_exp2l:
+; CHECK-LABEL: libcall1_exp2l:
 ; CHECK: ld $25, %call16(exp2l)
 
 define fp128 @libcall1_exp2l() {
@@ -308,7 +308,7 @@ entry:
 
 declare fp128 @exp2l(fp128) #2
 
-; CHECK: libcall1_logl:
+; CHECK-LABEL: libcall1_logl:
 ; CHECK: ld $25, %call16(logl)
 
 define fp128 @libcall1_logl() {
@@ -320,7 +320,7 @@ entry:
 
 declare fp128 @logl(fp128) #2
 
-; CHECK: libcall1_log2l:
+; CHECK-LABEL: libcall1_log2l:
 ; CHECK: ld $25, %call16(log2l)
 
 define fp128 @libcall1_log2l() {
@@ -332,7 +332,7 @@ entry:
 
 declare fp128 @log2l(fp128) #2
 
-; CHECK: libcall1_log10l:
+; CHECK-LABEL: libcall1_log10l:
 ; CHECK: ld $25, %call16(log10l)
 
 define fp128 @libcall1_log10l() {
@@ -344,7 +344,7 @@ entry:
 
 declare fp128 @log10l(fp128) #2
 
-; CHECK: libcall1_nearbyintl:
+; CHECK-LABEL: libcall1_nearbyintl:
 ; CHECK: ld $25, %call16(nearbyintl)
 
 define fp128 @libcall1_nearbyintl() {
@@ -356,7 +356,7 @@ entry:
 
 declare fp128 @nearbyintl(fp128) #1
 
-; CHECK: libcall1_floorl:
+; CHECK-LABEL: libcall1_floorl:
 ; CHECK: ld $25, %call16(floorl)
 
 define fp128 @libcall1_floorl() {
@@ -368,7 +368,7 @@ entry:
 
 declare fp128 @floorl(fp128) #1
 
-; CHECK: libcall1_sqrtl:
+; CHECK-LABEL: libcall1_sqrtl:
 ; CHECK: ld $25, %call16(sqrtl)
 
 define fp128 @libcall1_sqrtl() {
@@ -380,7 +380,7 @@ entry:
 
 declare fp128 @sqrtl(fp128) #2
 
-; CHECK: libcall1_rintl:
+; CHECK-LABEL: libcall1_rintl:
 ; CHECK: ld $25, %call16(rintl)
 
 define fp128 @libcall1_rintl() {
@@ -392,7 +392,7 @@ entry:
 
 declare fp128 @rintl(fp128) #1
 
-; CHECK: libcall_powil:
+; CHECK-LABEL: libcall_powil:
 ; CHECK: ld $25, %call16(__powitf2)
 
 define fp128 @libcall_powil(fp128 %a, i32 %b) {
@@ -403,7 +403,7 @@ entry:
 
 declare fp128 @llvm.powi.f128(fp128, i32) #3
 
-; CHECK:     libcall2_copysignl:
+; CHECK-LABEL:     libcall2_copysignl:
 ; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
 ; CHECK-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
 ; CHECK-DAG: ld     $[[R0:[0-9]+]], %got_disp(gld1)
@@ -426,7 +426,7 @@ entry:
 
 declare fp128 @copysignl(fp128, fp128) #1
 
-; CHECK: libcall2_powl:
+; CHECK-LABEL: libcall2_powl:
 ; CHECK: ld $25, %call16(powl)
 
 define fp128 @libcall2_powl() {
@@ -439,7 +439,7 @@ entry:
 
 declare fp128 @powl(fp128, fp128) #2
 
-; CHECK: libcall2_fmodl:
+; CHECK-LABEL: libcall2_fmodl:
 ; CHECK: ld $25, %call16(fmodl)
 
 define fp128 @libcall2_fmodl() {
@@ -452,7 +452,7 @@ entry:
 
 declare fp128 @fmodl(fp128, fp128) #2
 
-; CHECK: libcall3_fmal:
+; CHECK-LABEL: libcall3_fmal:
 ; CHECK: ld $25, %call16(fmal)
 
 define fp128 @libcall3_fmal() {
@@ -466,7 +466,7 @@ entry:
 
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4
 
-; CHECK: cmp_lt:
+; CHECK-LABEL: cmp_lt:
 ; CHECK: ld $25, %call16(__lttf2)
 
 define i32 @cmp_lt(fp128 %a, fp128 %b) {
@@ -476,7 +476,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_le:
+; CHECK-LABEL: cmp_le:
 ; CHECK: ld $25, %call16(__letf2)
 
 define i32 @cmp_le(fp128 %a, fp128 %b) {
@@ -486,7 +486,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_gt:
+; CHECK-LABEL: cmp_gt:
 ; CHECK: ld $25, %call16(__gttf2)
 
 define i32 @cmp_gt(fp128 %a, fp128 %b) {
@@ -496,7 +496,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ge:
+; CHECK-LABEL: cmp_ge:
 ; CHECK: ld $25, %call16(__getf2)
 
 define i32 @cmp_ge(fp128 %a, fp128 %b) {
@@ -506,7 +506,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_eq:
+; CHECK-LABEL: cmp_eq:
 ; CHECK: ld $25, %call16(__eqtf2)
 
 define i32 @cmp_eq(fp128 %a, fp128 %b) {
@@ -516,7 +516,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ne:
+; CHECK-LABEL: cmp_ne:
 ; CHECK: ld $25, %call16(__netf2)
 
 define i32 @cmp_ne(fp128 %a, fp128 %b) {
@@ -526,7 +526,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: load_LD_LD:
+; CHECK-LABEL: load_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $2, 0($[[R0]])
 ; CHECK: ld $4, 8($[[R0]])
@@ -537,7 +537,7 @@ entry:
   ret fp128 %0
 }
 
-; CHECK: load_LD_float:
+; CHECK-LABEL: load_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gf1)
 ; CHECK: lw   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extendsftf2)
@@ -550,7 +550,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: load_LD_double:
+; CHECK-LABEL: load_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gd1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extenddftf2)
@@ -563,7 +563,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: store_LD_LD:
+; CHECK-LABEL: store_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]])
@@ -578,7 +578,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_float:
+; CHECK-LABEL: store_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -595,7 +595,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_double:
+; CHECK-LABEL: store_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -612,7 +612,7 @@ entry:
   ret void
 }
 
-; CHECK: select_LD:
+; CHECK-LABEL: select_LD:
 ; CHECK: movn $8, $6, $4
 ; CHECK: movn $9, $7, $4
 ; CHECK: move $2, $8
@@ -625,7 +625,7 @@ entry:
   ret fp128 %cond
 }
 
-; CHECK: selectCC_LD:
+; CHECK-LABEL: selectCC_LD:
 ; CHECK: move $[[R0:[0-9]+]], $11
 ; CHECK: move $[[R1:[0-9]+]], $10
 ; CHECK: move $[[R2:[0-9]+]], $9
diff --git a/llvm/test/CodeGen/Mips/mips64-libcall.ll b/llvm/test/CodeGen/Mips/mips64-libcall.ll
index d54598be70d..290baafd18b 100644
--- a/llvm/test/CodeGen/Mips/mips64-libcall.ll
+++ b/llvm/test/CodeGen/Mips/mips64-libcall.ll
@@ -5,7 +5,7 @@
 
 ; Check that %add is not passed in an integer register.
 ;
-; HARD: callfloor:
+; HARD-LABEL: callfloor:
 ; HARD-NOT: dmfc1 $4
 
 define double @callfloor(double %d) nounwind readnone {
@@ -19,7 +19,7 @@ declare double @floor(double) nounwind readnone
 
 ; Check call16.
 ;
-; SOFT: f64add:
+; SOFT-LABEL: f64add:
 ; SOFT: ld $25, %call16(__adddf3)
 
 define double @f64add(double %a, double %b) {
diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll
index 2e3df3a0a85..7b06c2d7641 100644
--- a/llvm/test/CodeGen/Mips/mips64instrs.ll
+++ b/llvm/test/CodeGen/Mips/mips64instrs.ll
@@ -86,7 +86,7 @@ entry:
 
 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -96,7 +96,7 @@ entry:
 
 define i64 @f15(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -106,7 +106,7 @@ entry:
 
 define i64 @f16(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
@@ -116,7 +116,7 @@ entry:
 
 define i64 @f17(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
diff --git a/llvm/test/CodeGen/Mips/misha.ll b/llvm/test/CodeGen/Mips/misha.ll
index 80637edb167..65d3b7b5d87 100644
--- a/llvm/test/CodeGen/Mips/misha.ll
+++ b/llvm/test/CodeGen/Mips/misha.ll
@@ -25,10 +25,10 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %inc = add nsw i32 %i.010, 1
   %cmp = icmp eq i32 %inc, %conv
   br i1 %cmp, label %for.end, label %for.body
-; 16: sumc:
+; 16-LABEL: sumc:
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
-; 16: sum:
+; 16-LABEL: sum:
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 
diff --git a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index eae9a2216ac..be9d0b6b68c 100644
--- a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -8,16 +8,16 @@
 
 @g0 = common global double 0.000000e+00, align 8
 
-; LE-PIC: test_ldc1:
+; LE-PIC-LABEL: test_ldc1:
 ; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
 ; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
-; LE-STATIC: test_ldc1:
+; LE-STATIC-LABEL: test_ldc1:
 ; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_ldc1:
+; BE-PIC-LABEL: test_ldc1:
 ; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
 ; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_ldc1:
+; CHECK-LDC1-SDC1-LABEL: test_ldc1:
 ; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
 
 define double @test_ldc1() {
@@ -26,16 +26,16 @@ entry:
   ret double %0
 }
 
-; LE-PIC: test_sdc1:
+; LE-PIC-LABEL: test_sdc1:
 ; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
 ; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
-; LE-STATIC: test_sdc1:
+; LE-STATIC-LABEL: test_sdc1:
 ; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_sdc1:
+; BE-PIC-LABEL: test_sdc1:
 ; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
 ; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_sdc1:
+; CHECK-LDC1-SDC1-LABEL: test_sdc1:
 ; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
 
 define void @test_sdc1(double %a) {
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index 35332b6550d..10972e884ac 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -27,7 +27,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va1:
+; CHECK-LABEL: va1:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -53,7 +53,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va2:
+; CHECK-LABEL: va2:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -81,7 +81,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va3:
+; CHECK-LABEL: va3:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -104,7 +104,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va4:
+; CHECK-LABEL: va4:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: sw      $6, 32($sp)
@@ -132,7 +132,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va5:
+; CHECK-LABEL: va5:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: lw      $2, 36($sp)
@@ -158,7 +158,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va6:
+; CHECK-LABEL: va6:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 36
@@ -186,7 +186,7 @@ entry:
   %tmp = load i32* %c, align 4
   ret i32 %tmp
 
-; CHECK: va7:
+; CHECK-LABEL: va7:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: lw      $2, 40($sp)
 }
@@ -209,7 +209,7 @@ entry:
   %tmp = load double* %c, align 8
   ret double %tmp
 
-; CHECK: va8:
+; CHECK-LABEL: va8:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   ${{[0-9]+}}, $sp, 48
 ; CHECK: ldc1    $f0, 48($sp)
@@ -235,7 +235,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va9:
+; CHECK-LABEL: va9:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: lw      $2, 52($sp)
 }
@@ -260,7 +260,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va10:
+; CHECK-LABEL: va10:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 52
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
diff --git a/llvm/test/CodeGen/Mips/private.ll b/llvm/test/CodeGen/Mips/private.ll
index d1a67fd9f4b..058db0bb977 100644
--- a/llvm/test/CodeGen/Mips/private.ll
+++ b/llvm/test/CodeGen/Mips/private.ll
@@ -3,14 +3,14 @@
 ; RUN: llc -march=mips < %s | FileCheck %s
 
 define private void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   ret void
 }
 
 @baz = private global i32 4
 
 define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: call16($foo)
 ; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
 ; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
diff --git a/llvm/test/CodeGen/Mips/return-vector.ll b/llvm/test/CodeGen/Mips/return-vector.ll
index 6bb9523ffb1..0e0d5158754 100644
--- a/llvm/test/CodeGen/Mips/return-vector.ll
+++ b/llvm/test/CodeGen/Mips/return-vector.ll
@@ -30,7 +30,7 @@ entry:
   %add7 = add i32 %add5, %add6
   ret i32 %add7
 
-; CHECK:        call_i8:
+; CHECK-LABEL:        call_i8:
 ; CHECK:        call16(i8)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        lw      $[[R0:[a-z0-9]+]], 60($sp)
@@ -56,7 +56,7 @@ entry:
   %add3 = fadd float %add1, %add2
   ret float %add3
 
-; CHECK:        call_f4:
+; CHECK-LABEL:        call_f4:
 ; CHECK:        call16(f4)
 ; CHECK:        addiu   $4, $sp, 16
 ; CHECK:        lwc1    $[[R0:[a-z0-9]+]], 28($sp)
@@ -78,7 +78,7 @@ entry:
   %add3 = fadd double %add1, %add2
   ret double %add3
 
-; CHECK:        call_d4:
+; CHECK-LABEL:        call_d4:
 ; CHECK:        call16(d4)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        ldc1    $[[R0:[a-z0-9]+]], 56($sp)
@@ -109,7 +109,7 @@ entry:
   %add3 = add i32 %add1, %add2
   ret i32 %add3
 
-; CHECK:        call_i4:
+; CHECK-LABEL:        call_i4:
 ; CHECK:        call16(i4)
 ; CHECK-NOT:    lw
 ; CHECK:        addu    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -126,7 +126,7 @@ entry:
   %add1 = fadd float %v0, %v1
   ret float %add1
 
-; CHECK:        call_f2:
+; CHECK-LABEL:        call_f2:
 ; CHECK:        call16(f2)
 ; CHECK-NOT:    lwc1
 ; CHECK:        add.s    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -141,7 +141,7 @@ entry:
   %add1 = fadd double %v0, %v1
   ret double %add1
 
-; CHECK:        call_d2:
+; CHECK-LABEL:        call_d2:
 ; CHECK:        call16(d2)
 ; CHECK-NOT:    ldc1
 ; CHECK:        add.d    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -158,7 +158,7 @@ define <8 x i32> @return_i8() {
 entry:
   ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 
-; CHECK:        return_i8:
+; CHECK-LABEL:        return_i8:
 ; CHECK:        sw      $[[R0:[a-z0-9]+]], 28($4)
 ; CHECK:        sw      $[[R1:[a-z0-9]+]], 24($4)
 ; CHECK:        sw      $[[R2:[a-z0-9]+]], 20($4)
@@ -178,7 +178,7 @@ entry:
   %vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
   ret <4 x float> %vecins4
 
-; CHECK:        return_f4:
+; CHECK-LABEL:        return_f4:
 ; CHECK-DAG:    lwc1    $[[R0:[a-z0-9]+]], 16($sp)
 ; CHECK-DAG:    swc1    $[[R0]], 12($4)
 ; CHECK-DAG:    sw      $7, 8($4)
@@ -195,7 +195,7 @@ entry:
   %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
   ret <4 x double> %vecins4
 
-; CHECK:            return_d4:
+; CHECK-LABEL:            return_d4:
 ; CHECK-DAG:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
 ; CHECK-DAG:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
 ; CHECK-DAG:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
@@ -212,7 +212,7 @@ define <4 x i32> @return_i4() {
 entry:
   ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 
-; CHECK:        return_i4:
+; CHECK-LABEL:        return_i4:
 ; CHECK:        addiu   $2, $zero, 0
 ; CHECK:        addiu   $3, $zero, 1
 ; CHECK:        addiu   $4, $zero, 2
@@ -226,7 +226,7 @@ entry:
   %vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
   ret <2 x float> %vecins2
 
-; CHECK:        return_f2:
+; CHECK-LABEL:        return_f2:
 ; CHECK:        mov.s   $f0, $f12
 ; CHECK:        mov.s   $f2, $f14
 }
@@ -238,7 +238,7 @@ entry:
   %vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
   ret <2 x double> %vecins2
 
-; CHECK:        return_d2:
+; CHECK-LABEL:        return_d2:
 ; CHECK:        mov.d   $f0, $f12
 ; CHECK:        mov.d   $f2, $f14
 }
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll
index 284cd355853..50ee860a971 100644
--- a/llvm/test/CodeGen/Mips/setcc-se.ll
+++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32
 
-; CHECK: seteq0:
+; CHECK-LABEL: seteq0:
 ; CHECK: sltiu ${{[0-9]+}}, $4, 1
 
 define i32 @seteq0(i32 %a) {
@@ -12,7 +12,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: setne0:
+; CHECK-LABEL: setne0:
 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
 
 define i32 @setne0(i32 %a) {
@@ -22,7 +22,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: slti_beq0:
+; CHECK-LABEL: slti_beq0:
 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
 ; CHECK: beq $[[R0]], $zero
 
@@ -39,7 +39,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq1:
+; CHECK-LABEL: slti_beq1:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq1(i32 %a) {
@@ -55,7 +55,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq2:
+; CHECK-LABEL: slti_beq2:
 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
 ; CHECK: beq $[[R0]], $zero
 
@@ -72,7 +72,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq3:
+; CHECK-LABEL: slti_beq3:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq3(i32 %a) {
@@ -88,7 +88,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq0:
+; CHECK-LABEL: sltiu_beq0:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
 ; CHECK: beq $[[R0]], $zero
 
@@ -105,7 +105,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq1:
+; CHECK-LABEL: sltiu_beq1:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq1(i32 %a) {
@@ -121,7 +121,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq2:
+; CHECK-LABEL: sltiu_beq2:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
 ; CHECK: beq $[[R0]], $zero
 
@@ -138,7 +138,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq3:
+; CHECK-LABEL: sltiu_beq3:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq3(i32 %a) {
diff --git a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
index 23a8aeae91a..c44ea080a88 100644
--- a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
+++ b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
@@ -4,7 +4,7 @@
 @gint_ = external global i32
 @gLL_ = external global i64
 
-; 32: store_int_float_:
+; 32-LABEL: store_int_float_:
 ; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
 
@@ -15,10 +15,10 @@ entry:
   ret void
 }
 
-; 32: store_int_double_:
+; 32-LABEL: store_int_double_:
 ; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
-; 64: store_int_double_:
+; 64-LABEL: store_int_double_:
 ; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: swc1 $f[[R0]],
 
@@ -29,7 +29,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_float_:
+; 64-LABEL: store_LL_float_:
 ; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
@@ -40,7 +40,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_double_:
+; 64-LABEL: store_LL_double_:
 ; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
diff --git a/llvm/test/CodeGen/Mips/stackcoloring.ll b/llvm/test/CodeGen/Mips/stackcoloring.ll
index 76cc08679d6..4987dad5338 100644
--- a/llvm/test/CodeGen/Mips/stackcoloring.ll
+++ b/llvm/test/CodeGen/Mips/stackcoloring.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32*
 
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 ; CHECK: lw ${{[0-9]+}}, %got(g1)
 ; CHECK: # %for.body
 ; CHECK: # %for.end
diff --git a/llvm/test/CodeGen/Mips/stchar.ll b/llvm/test/CodeGen/Mips/stchar.ll
index c00c9fd9d2a..12eae3487ff 100644
--- a/llvm/test/CodeGen/Mips/stchar.ll
+++ b/llvm/test/CodeGen/Mips/stchar.ll
@@ -50,8 +50,8 @@ entry:
   %conv1.i = sext i8 %3 to i32
   %call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
   ret void
-; 16_b: test:
-; 16_h: test:
+; 16_b-LABEL: test:
+; 16_h-LABEL: test:
 ; 16_b:	sb	${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
 ; 16_b: lb      ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
 ; 16_h:	sh	${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/tls-models.ll b/llvm/test/CodeGen/Mips/tls-models.ll
index 8f5789ec799..1a958dceaa2 100644
--- a/llvm/test/CodeGen/Mips/tls-models.ll
+++ b/llvm/test/CodeGen/Mips/tls-models.ll
@@ -20,9 +20,9 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; CHECK-NONPIC:   f1:
+  ; CHECK-NONPIC-LABEL:   f1:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f1:
+  ; CHECK-PIC-LABEL:      f1:
   ; CHECK-PIC:      %tlsgd
 }
 
@@ -31,9 +31,9 @@ entry:
   ret i32* @internal_gd
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f2:
+  ; CHECK-NONPIC-LABEL:   f2:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f2:
+  ; CHECK-PIC-LABEL:      f2:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -45,9 +45,9 @@ entry:
   ret i32* @external_ld
 
   ; Non-PIC code can use initial exec, PIC should use local dynamic.
-  ; CHECK-NONPIC:   f3:
+  ; CHECK-NONPIC-LABEL:   f3:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f3:
+  ; CHECK-PIC-LABEL:      f3:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -56,9 +56,9 @@ entry:
   ret i32* @internal_ld
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f4:
+  ; CHECK-NONPIC-LABEL:   f4:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f4:
+  ; CHECK-PIC-LABEL:      f4:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -70,9 +70,9 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; CHECK-NONPIC:   f5:
+  ; CHECK-NONPIC-LABEL:   f5:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f5:
+  ; CHECK-PIC-LABEL:      f5:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -81,9 +81,9 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; CHECK-NONPIC:   f6:
+  ; CHECK-NONPIC-LABEL:   f6:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f6:
+  ; CHECK-PIC-LABEL:      f6:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -95,9 +95,9 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f7:
+  ; CHECK-NONPIC-LABEL:   f7:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f7:
+  ; CHECK-PIC-LABEL:      f7:
   ; CHECK-PIC:      %tprel_hi
 }
 
@@ -106,8 +106,8 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f8:
+  ; CHECK-NONPIC-LABEL:   f8:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f8:
+  ; CHECK-PIC-LABEL:      f8:
   ; CHECK-PIC:      %tprel_hi
 }
diff --git a/llvm/test/CodeGen/Mips/tls.ll b/llvm/test/CodeGen/Mips/tls.ll
index d83edfd9fa1..23a8f93a9d7 100644
--- a/llvm/test/CodeGen/Mips/tls.ll
+++ b/llvm/test/CodeGen/Mips/tls.ll
@@ -13,14 +13,14 @@ entry:
   %tmp = load i32* @t1, align 4
   ret i32 %tmp
 
-; PIC:       f1:
+; PIC-LABEL:       f1:
 ; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
 ; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
 ; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
 ; PIC-DAG:   jalr    $25
 ; PIC-DAG:   lw      $2, 0($2)
 
-; STATIC:   f1:
+; STATIC-LABEL:   f1:
 ; STATIC:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
 ; STATIC:   rdhwr   $3, $29
@@ -36,19 +36,19 @@ entry:
   %tmp = load i32* @t2, align 4
   ret i32 %tmp
 
-; PIC:       f2:
+; PIC-LABEL:       f2:
 ; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
 ; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
 ; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
 ; PIC-DAG:   jalr    $25
 ; PIC-DAG:   lw      $2, 0($2)
 
-; STATICGP: f2:
+; STATICGP-LABEL: f2:
 ; STATICGP: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATICGP: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATICGP: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
 
-; STATIC:   f2:
+; STATIC-LABEL:   f2:
 ; STATIC:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATIC:   rdhwr   $3, $29
@@ -61,7 +61,7 @@ entry:
 
 define i32 @f3() nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 
 ; PIC:   addiu   $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
 ; PIC:   jalr    $25
diff --git a/llvm/test/CodeGen/Mips/tnaked.ll b/llvm/test/CodeGen/Mips/tnaked.ll
index f5bdd915b28..edf1ecfd75c 100644
--- a/llvm/test/CodeGen/Mips/tnaked.ll
+++ b/llvm/test/CodeGen/Mips/tnaked.ll
@@ -7,7 +7,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnaked
-; CHECK:          tnaked: 
+; CHECK-LABEL:          tnaked:
 ; CHECK-NOT:	.frame	{{.*}}
 ; CHECK-NOT:     .mask 	{{.*}}
 ; CHECK-NOT:	.fmask	{{.*}}
@@ -19,7 +19,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnonaked
-; CHECK:         tnonaked: 
+; CHECK-LABEL:         tnonaked:
 ; CHECK:	.frame	$fp,8,$ra
 ; CHECK:        .mask 	0x40000000,-4
 ; CHECK:	.fmask	0x00000000,0