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-rw-r--r--llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll80
1 files changed, 40 insertions, 40 deletions
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
index 9f2f0661f99..a5fe34c1f68 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
@@ -1,6 +1,6 @@
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -17,7 +17,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -34,7 +34,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
@@ -51,7 +51,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -68,7 +68,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -85,7 +85,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
@@ -102,7 +102,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -119,7 +119,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -136,7 +136,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
@@ -153,7 +153,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -170,7 +170,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -187,7 +187,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
@@ -204,7 +204,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -221,7 +221,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -238,7 +238,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -255,7 +255,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -272,7 +272,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -289,7 +289,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -306,7 +306,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -323,7 +323,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -340,7 +340,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -355,7 +355,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -370,7 +370,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -385,7 +385,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -400,7 +400,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -415,7 +415,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -430,7 +430,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -445,7 +445,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -460,7 +460,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -475,7 +475,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -490,7 +490,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -505,7 +505,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
@@ -520,7 +520,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -535,7 +535,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -550,7 +550,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -565,7 +565,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -580,7 +580,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -595,7 +595,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -610,7 +610,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
@@ -625,7 +625,7 @@ entry:
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
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