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authorSimon Atanasyan <simon@atanasyan.com>2019-07-09 15:48:05 +0000
committerSimon Atanasyan <simon@atanasyan.com>2019-07-09 15:48:05 +0000
commit623282f0dd7fb1dba7623f2b10294f003f92570e (patch)
tree50ef8579d1ec548ed23c7b26ddd95254dcba78d4 /llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
parent901d91e5f0f5dc1c449b60b97af1adaf5c928eb9 (diff)
downloadbcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.tar.gz
bcm5719-llvm-623282f0dd7fb1dba7623f2b10294f003f92570e.zip
[mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture was added in `MIPS32 R2`. llvm-svn: 365507
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll')
-rw-r--r--llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
index c10c206255f..7d44620e257 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
@@ -1,8 +1,8 @@
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format).
-; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind {
entry:
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