[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876

5 files changed, 37 insertions, 15 deletions

diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
index b7aad049e8a..16a7b067e11 100644
--- a/llvm/test/CodeGen/Mips/countleading.ll
+++ b/llvm/test/CodeGen/Mips/countleading.ll
@@ -4,7 +4,8 @@
 ; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
-; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS64 %s
 
 ; Prefixes:
 ;   ALL      - All
@@ -21,6 +22,8 @@ entry:
 
 ; MIPS64-GT-R1:  clz $2, $4
 
+; MICROMIPS64:   clz $2, $4
+
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
   ret i32 %tmp1
 }
@@ -37,6 +40,8 @@ entry:
 
 ; MIPS64-GT-R1:  clo $2, $4
 
+; MICROMIPS64:   clo $2, $4
+
   %neg = xor i32 %X, -1
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
   ret i32 %tmp1
@@ -58,6 +63,7 @@ entry:
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
+; MICROMIPS64:   dclz $2, $4
 
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
@@ -83,6 +89,7 @@ entry:
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclo $2, $4
+; MICROMIPS64:   dclo $2, $4
 
   %neg = xor i64 %X, -1
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index 52c6f906639..e3d314946f6 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -1,64 +1,65 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsllv
+; ALL: dsllv
   %shl = shl i64 %a0, %a1
   ret i64 %shl
 }
 
 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrav
+; ALL: dsrav
   %shr = ashr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
 entry:
-; CHECK: dsrlv
+; ALL: dsrlv
   %shr = lshr i64 %a0, %a1
   ret i64 %shr
 }
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shl = shl i64 %a0, 10
   ret i64 %shl
 }
 
 define i64 @f4(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = ashr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f5(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f6(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shl = shl i64 %a0, 40
   ret i64 %shl
 }
 
 define i64 @f7(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = ashr i64 %a0, 40
   ret i64 %shr
 }
 
 define i64 @f8(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
+; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
   %shr = lshr i64 %a0, 40
   ret i64 %shr
 }
@@ -66,7 +67,7 @@ entry:
 define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shr = lshr i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shl = shl i64 %a0, %sub
@@ -77,7 +78,7 @@ entry:
 define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
 entry:
 ; CHECK-NOT:  sll
-; CHECK:      drotrv
+; ALL:      drotrv
   %shl = shl i64 %a0, %a1
   %sub = sub i64 64, %a1
   %shr = lshr i64 %a0, %sub
@@ -87,7 +88,7 @@ entry:
 
 define i64 @f11(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
+; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   %shl = shl i64 %a0, 54
   %or = or i64 %shr, %shl
@@ -96,7 +97,7 @@ entry:
 
 define i64 @f12(i64 %a0) nounwind readnone {
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; ALL:       drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
   %shl = shl i64 %a0, 10
   %shr = lshr i64 %a0, 54
   %or = or i64 %shl, %shr
diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
index 9d88e3e5c9d..e7b81656b19 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -284,3 +284,8 @@
 0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
 0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
 0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4
+0x58 0x22 0x4b 0x3c # CHECK: dclo $1, $2
+0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2
+0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
+0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4
+0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4
diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s
index a39e20cd5df..ec45b7907d1 100644
--- a/llvm/test/MC/Mips/micromips64r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips64r6/invalid.s
@@ -287,3 +287,7 @@
   xori $3, -1                  # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   xori $3, 65536               # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
   not $3, 4                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  drotr $5, $10, 64            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr $5, $10, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
+  drotr32 $1, $2, 32           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
+  drotr32 $1, $2, -1           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s
index 5ad3aa4cf69..8936a59f65f 100644
--- a/llvm/test/MC/Mips/micromips64r6/valid.s
+++ b/llvm/test/MC/Mips/micromips64r6/valid.s
@@ -295,5 +295,10 @@ a:
         xor $3, $4, 5            # CHECK: xori $3, $4, 5          # encoding: [0x70,0x64,0x00,0x05]
         xor $3, $4, $5           # CHECK: xor $3, $4, $5          # encoding: [0x00,0xa4,0x1b,0x10]
         xori $3, $4, 1234        # CHECK: xori $3, $4, 1234       # encoding: [0x70,0x64,0x04,0xd2]
+        dclo $1, $2              # CHECK: dclo $1, $2             # encoding: [0x58,0x22,0x4b,0x3c]
+        dclz $1, $2              # CHECK: dclz $1, $2             # encoding: [0x58,0x22,0x5b,0x3c]
+        drotr $5, $10, 8         # CHECK: drotr $5, $10, 8        # encoding: [0x58,0xaa,0x40,0xc0]
+        drotr32 $1, $2, 4        # CHECK: drotr32 $1, $2, 4       # encoding: [0x58,0x22,0x20,0xc8]
+        drotrv $3, $6, $4        # CHECK: drotrv $3, $6, $4       # encoding: [0x58,0xc4,0x18,0xd0]
 
 1: