From 32177d6becc390a942ae07285484b088755f2747 Mon Sep 17 00:00:00 2001 From: Vasileios Kalintiris Date: Tue, 21 Apr 2015 10:49:03 +0000 Subject: [mips] Optimize code generation for 64-bit variable shift instructions. Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376 --- llvm/test/CodeGen/Mips/mips64shift.ll | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'llvm/test/CodeGen/Mips/mips64shift.ll') diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll index 45d1c953227..52c6f906639 100644 --- a/llvm/test/CodeGen/Mips/mips64shift.ll +++ b/llvm/test/CodeGen/Mips/mips64shift.ll @@ -65,7 +65,8 @@ entry: define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shr = lshr i64 %a0, %a1 %sub = sub i64 64, %a1 %shl = shl i64 %a0, %sub @@ -75,7 +76,8 @@ entry: define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shl = shl i64 %a0, %a1 %sub = sub i64 64, %a1 %shr = lshr i64 %a0, %sub -- cgit v1.2.3