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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-01 14:53:53 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-01 14:53:53 +0000 |
| commit | bd2715475702e6b178e8db2101c8335e305ef787 (patch) | |
| tree | 0b29d29a9d1e49e625bba9112a4d500d093b4ffb /llvm/test/CodeGen/Mips/longbranch.ll | |
| parent | fbd3de7851b5874c282c34d9077f470c344e3870 (diff) | |
| download | bcm5719-llvm-bd2715475702e6b178e8db2101c8335e305ef787.tar.gz bcm5719-llvm-bd2715475702e6b178e8db2101c8335e305ef787.zip | |
[mips] interAptiv based generic schedule model
This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.
Reviewers: vkalintiris, dsanders
Differential Revision: https://reviews.llvm.org/D23551
llvm-svn: 280374
Diffstat (limited to 'llvm/test/CodeGen/Mips/longbranch.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/longbranch.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/longbranch.ll b/llvm/test/CodeGen/Mips/longbranch.ll index 59e284165d4..11bc6d39031 100644 --- a/llvm/test/CodeGen/Mips/longbranch.ll +++ b/llvm/test/CodeGen/Mips/longbranch.ll @@ -102,8 +102,8 @@ end: ; N64: [[BB0]]: ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) -; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: addiu $[[R3:[0-9]+]], $zero, 1 +; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: sw $[[R3]], 0($[[R2]]) ; N64: [[BB2]]: ; N64: jr $ra |
