From bd2715475702e6b178e8db2101c8335e305ef787 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 1 Sep 2016 14:53:53 +0000 Subject: [mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374 --- llvm/test/CodeGen/Mips/longbranch.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/test/CodeGen/Mips/longbranch.ll') diff --git a/llvm/test/CodeGen/Mips/longbranch.ll b/llvm/test/CodeGen/Mips/longbranch.ll index 59e284165d4..11bc6d39031 100644 --- a/llvm/test/CodeGen/Mips/longbranch.ll +++ b/llvm/test/CodeGen/Mips/longbranch.ll @@ -102,8 +102,8 @@ end: ; N64: [[BB0]]: ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) -; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: addiu $[[R3:[0-9]+]], $zero, 1 +; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: sw $[[R3]], 0($[[R2]]) ; N64: [[BB2]]: ; N64: jr $ra -- cgit v1.2.3