[mips] Define certain instructions in microMIPS32r3

Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d

These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.

Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.

Differential revision: https://reviews.llvm.org/D42738

llvm-svn: 324584

3 files changed, 122 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
new file mode 100644
index 00000000000..33a86bbc5de
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
@@ -0,0 +1,55 @@
+; RUN: llc -march=mips -mcpu=mips32                           -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+
+define double @add_d(double %a, double %b) {
+; MIPS32:     add.d   {{.*}}         # <MCInst #{{[0-9]+}} FADD_D32
+; MIPS32FP64: add.d   {{.*}}         # <MCInst #{{[0-9]+}} FADD_D64
+; MM:         add.d   {{.*}}         # <MCInst #{{[0-9]+}} FADD_D32_MM
+; MMFP64:     add.d   {{.*}}         # <MCInst #{{[0-9]+}} FADD_D64_MM
+; MMR6:       add.d   {{.*}}         # <MCInst #{{[0-9]+}} FADD_D64_MM
+    %1 = fadd double %a, %b
+    ret double %1
+}
+
+define double @sub_d(double %a, double %b) {
+; MIPS32:     sub.d   {{.*}}         # <MCInst #{{[0-9]+}} FSUB_D32
+; MIPS32FP64: sub.d   {{.*}}         # <MCInst #{{[0-9]+}} FSUB_D64
+; MM:         sub.d   {{.*}}         # <MCInst #{{[0-9]+}} FSUB_D32_MM
+; MMFP64:     sub.d   {{.*}}         # <MCInst #{{[0-9]+}} FSUB_D64_MM
+; MMR6:       sub.d   {{.*}}         # <MCInst #{{[0-9]+}} FSUB_D64_MM
+    %1 = fsub double %a, %b
+    ret double %1
+}
+
+define double @mul_d(double %a, double %b) {
+; MIPS32:     mul.d   {{.*}}         # <MCInst #{{[0-9]+}} FMUL_D32
+; MIPS32FP64: mul.d   {{.*}}         # <MCInst #{{[0-9]+}} FMUL_D64
+; MM:         mul.d   {{.*}}         # <MCInst #{{[0-9]+}} FMUL_D32_MM
+; MMFP64:     mul.d   {{.*}}         # <MCInst #{{[0-9]+}} FMUL_D64_MM
+; MMR6:       mul.d   {{.*}}         # <MCInst #{{[0-9]+}} FMUL_D64_MM
+    %1 = fmul double %a, %b
+    ret double %1
+}
+
+define double @div_d(double %a, double %b) {
+; MIPS32:     div.d   {{.*}}         # <MCInst #{{[0-9]+}} FDIV_D32
+; MIPS32FP64: div.d   {{.*}}         # <MCInst #{{[0-9]+}} FDIV_D64
+; MM:         div.d   {{.*}}         # <MCInst #{{[0-9]+}} FDIV_D32_MM
+; MMFP64:     div.d   {{.*}}         # <MCInst #{{[0-9]+}} FDIV_D64_MM
+; MMR6:       div.d   {{.*}}         # <MCInst #{{[0-9]+}} FDIV_D64_MM
+    %1 = fdiv double %a, %b
+    ret double %1
+}
+
+define double @fneg(double %a) {
+; MIPS32:     neg.d   {{.*}}         # <MCInst #{{[0-9]+}} FNEG_D32
+; MIPS32FP64: neg.d   {{.*}}         # <MCInst #{{[0-9]+}} FNEG_D64
+; MM:         neg.d   {{.*}}         # <MCInst #{{[0-9]+}} FNEG_D32_MM
+; MMFP64:     neg.d   {{.*}}         # <MCInst #{{[0-9]+}} FNEG_D64_MM
+; MMR6:       neg.d   {{.*}}         # <MCInst #{{[0-9]+}} FNEG_D64_MM
+    %1 = fsub double -0.000000e+00, %a
+    ret double %1
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
new file mode 100644
index 00000000000..6593103de8d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
@@ -0,0 +1,30 @@
+; RUN: llc -march=mips -mcpu=mips32r2                         -asm-show-inst \
+; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32R2
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64            -asm-show-inst \
+; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips       -asm-show-inst \
+; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \
+; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips       -asm-show-inst \
+; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMR6
+
+define double @mthc1(i64 %a) {
+; MIPS32R2:   mthc1   {{.*}}                 # <MCInst #{{[0-9]+}} MTHC1_D32
+; MIPS32FP64: mthc1   {{.*}}                 # <MCInst #{{[0-9]+}} MTHC1_D64
+; MM:         mthc1   {{.*}}                 # <MCInst #{{[0-9]+}} MTHC1_D32_MM
+; MMFP64:     mthc1   {{.*}}                 # <MCInst #{{[0-9]+}} MTHC1_D64_MM
+; MMR6:       mthc1   {{.*}}                 # <MCInst #{{[0-9]+}} MTHC1_D64_MM
+    %1 = bitcast i64 %a to double
+    ret double %1
+}
+
+define i64 @mfhc1(double %a) {
+; MIPS32R2:   mfhc1   {{.*}}                 # <MCInst #{{[0-9]+}} MFHC1_D32
+; MIPS32FP64: mfhc1   {{.*}}                 # <MCInst #{{[0-9]+}} MFHC1_D64
+; MM:         mfhc1   {{.*}}                 # <MCInst #{{[0-9]+}} MFHC1_D32_MM
+; MMFP64:     mfhc1   {{.*}}                 # <MCInst #{{[0-9]+}} MFHC1_D64_MM
+; MMR6:       mfhc1   {{.*}}                 # <MCInst #{{[0-9]+}} MFHC1_D64_MM
+    %1 = bitcast double %a to i64
+    ret i64 %1
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
new file mode 100644
index 00000000000..04368f202fa
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=mips -mcpu=mips32                           -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips       -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+
+; TODO: Test for cvt_w_d is missing, could not generate instruction
+
+define double @cvt_d_s(float %a) {
+; MIPS32:     cvt.d.s {{.*}}               # <MCInst #{{[0-9]+}} CVT_D32_S
+; MIPS32FP64: cvt.d.s {{.*}}               # <MCInst #{{[0-9]+}} CVT_D64_S
+; MM:         cvt.d.s {{.*}}               # <MCInst #{{[0-9]+}} CVT_D32_S_MM
+; MMFP64:     cvt.d.s {{.*}}               # <MCInst #{{[0-9]+}} CVT_D64_S_MM
+; MMR6:       cvt.d.s {{.*}}               # <MCInst #{{[0-9]+}} CVT_D64_S_MM
+    %1 = fpext float %a to double
+    ret double %1
+}
+
+define double @cvt_d_w(i32 %a) {
+; MIPS32:     cvt.d.w {{.*}}                # <MCInst #{{[0-9]+}} CVT_D32_W
+; MIPS32FP64: cvt.d.w {{.*}}                # <MCInst #{{[0-9]+}} CVT_D64_W
+; MM:         cvt.d.w {{.*}}                # <MCInst #{{[0-9]+}} CVT_D32_W_MM
+; MMFP64:     cvt.d.w {{.*}}                # <MCInst #{{[0-9]+}} CVT_D64_W_MM
+; MMR6:       cvt.d.w {{.*}}                # <MCInst #{{[0-9]+}} CVT_D64_W_MM
+    %1 = sitofp i32 %a to double
+    ret double %1
+}
+
+define float @cvt_s_d(double %a) {
+; MIPS32:     cvt.s.d {{.*}}               # <MCInst #{{[0-9]+}} CVT_S_D32
+; MIPS32FP64: cvt.s.d {{.*}}               # <MCInst #{{[0-9]+}} CVT_S_D64
+; MM:         cvt.s.d {{.*}}               # <MCInst #{{[0-9]+}} CVT_S_D32_MM
+; MMFP64:     cvt.s.d {{.*}}               # <MCInst #{{[0-9]+}} CVT_S_D64_MM
+; MMR6:       cvt.s.d {{.*}}               # <MCInst #{{[0-9]+}} CVT_S_D64_MM
+     %1 = fptrunc double %a to float
+     ret float %1
+}