diff options
| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-08 09:25:17 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-08 09:25:17 +0000 |
| commit | b3e7ed3b941b3477b7797860eb99cb5154ba015e (patch) | |
| tree | 0ad069284c49ea0e3c4cea9eeed2db247febe326 | |
| parent | 820553fdb1e0cb49ac99a66bc5fd078283bb1a60 (diff) | |
| download | bcm5719-llvm-b3e7ed3b941b3477b7797860eb99cb5154ba015e.tar.gz bcm5719-llvm-b3e7ed3b941b3477b7797860eb99cb5154ba015e.zip | |
[mips] Define certain instructions in microMIPS32r3
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d
These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.
Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.
Differential revision: https://reviews.llvm.org/D42738
llvm-svn: 324584
37 files changed, 738 insertions, 254 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 7fa24062a62..f1a7f7852e1 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -119,7 +119,6 @@ class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>; class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>; class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>; class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>; -class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>; class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>; class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>; class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>; @@ -131,7 +130,6 @@ class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>; class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>; class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>; class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>; -class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>; class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>; class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>; class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; @@ -238,21 +236,15 @@ class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; /// Floating Point Instructions class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; -class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; -class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; -class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; -class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; -class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; -class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; @@ -265,11 +257,7 @@ class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; -class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; -class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; -class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; -class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; @@ -744,12 +732,6 @@ class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>; class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd, II_MTHC0>; -class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, - GPR32Opnd, II_MTC1>, - HARDFLOAT, FGR_32; -class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, - GPR32Opnd, II_MTC1>, - HARDFLOAT, FGR_64; class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd, II_MTC2>; @@ -793,10 +775,6 @@ class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>; class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd, II_MFHC0>; -class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, - II_MFHC1>, HARDFLOAT, FGR_32; -class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, - II_MFHC1>, HARDFLOAT, FGR_64; class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd, II_MFC2>; @@ -865,20 +843,12 @@ class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC, } class FADD_S_MMR6_DESC : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>; -class FADD_D_MMR6_DESC - : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>; class FSUB_S_MMR6_DESC : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>; -class FSUB_D_MMR6_DESC - : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>; class FMUL_S_MMR6_DESC : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>; -class FMUL_D_MMR6_DESC - : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>; class FDIV_S_MMR6_DESC : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>; -class FDIV_D_MMR6_DESC - : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>; class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>, HARDFLOAT; class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, @@ -901,12 +871,8 @@ class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC, } class FMOV_S_MMR6_DESC : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>; -class FMOV_D_MMR6_DESC - : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>; class FNEG_S_MMR6_DESC : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>; -class FNEG_D_MMR6_DESC - : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>; class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>, HARDFLOAT; @@ -944,16 +910,8 @@ class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>; class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>; -class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd, - II_CVT>; -class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd, - II_CVT>; -class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd, - II_CVT>; class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, FGR_64; -class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd, - II_CVT>; class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>; class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd, @@ -1414,22 +1372,11 @@ def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6; def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6; def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6; def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6; -def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6; -let DecoderNamespace = "MicroMipsFP64" in { - def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC, - ISA_MICROMIPS32R6; -} def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6; def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6; def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6; def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6; def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6; -def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC, - ISA_MICROMIPS32R6; -let DecoderNamespace = "MicroMipsFP64" in { - def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC, - ISA_MICROMIPS32R6; -} def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6; def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6; def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6; @@ -1478,20 +1425,12 @@ let DecoderMethod = "DecodeMemMMImm16" in { /// Floating Point Instructions def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC, - ISA_MICROMIPS32R6; def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC, - ISA_MICROMIPS32R6; def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC, - ISA_MICROMIPS32R6; def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC, - ISA_MICROMIPS32R6; def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC, ISA_MICROMIPS32R6; def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC, @@ -1502,12 +1441,8 @@ def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC, ISA_MICROMIPS32R6; def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC, - ISA_MICROMIPS32R6; def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC, ISA_MICROMIPS32R6; -def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC, - ISA_MICROMIPS32R6; def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6; def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1526,16 +1461,8 @@ def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC, ISA_MICROMIPS32R6; def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC, ISA_MICROMIPS32R6; -def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC, - ISA_MICROMIPS32R6; -def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC, - ISA_MICROMIPS32R6; -def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC, - ISA_MICROMIPS32R6; def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC, ISA_MICROMIPS32R6; -def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC, - ISA_MICROMIPS32R6; def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC, ISA_MICROMIPS32R6; def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC, diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index ce1cf3013fd..ac805caca58 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -11,7 +11,18 @@ // //===----------------------------------------------------------------------===// -let isCodeGenOnly = 1 in { +multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm, + SDPatternOperator OpNode = null_frag> { + def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, + FGR_32 { + string DecoderNamespace = "MicroMips"; + } + // FIXME: This needs to be part of the instruction mapping tables. + def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { + string DecoderNamespace = "MicroMipsFP64"; + } +} + def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS; def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, @@ -21,15 +32,16 @@ def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS; -def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, - ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; -def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>, - ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; -def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>, - ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; -def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, - ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; +defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>, + ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS; +defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>, + ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS; +defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>, + ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS; +defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>, + ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS; +let isCodeGenOnly = 1 in { def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6; def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, @@ -76,8 +88,6 @@ def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; -def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, - ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, @@ -91,6 +101,14 @@ def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64; } +let DecoderNamespace = "MicroMips" in { + def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, + ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32; +} +let DecoderNamespace = "MicroMipsFP64" in { + def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>, + ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64; +} multiclass ABSS_MMM<string opstr, InstrItinClass Itin, SDPatternOperator OpNode = null_frag> { @@ -113,26 +131,39 @@ let DecoderNamespace = "MicroMips" in { ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; } -let isCodeGenOnly = 1 in { def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, ABS_FM_MM<0, 0x1>, ISA_MICROMIPS; def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS; -def CVT_D_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; -def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; -def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, - ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; + +let DecoderNamespace = "MicroMips" in { + def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32; + def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32; +} + +let DecoderNamespace = "MicroMipsFP64" in { + def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64; + def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, + ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64; + def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, + ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64; +} + +let DecoderNamespace = "MicroMips" in { + def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, + ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32; +} + def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS; -def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, - ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32; - -def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABS_FM_MM<1, 0x1>, ISA_MICROMIPS, FGR_32; +defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>; +defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>; +let isCodeGenOnly = 1 in { def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>, ISA_MICROMIPS32_NOT_MIPS32R6; @@ -196,10 +227,20 @@ def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS { string DecoderNamespace = "MicroMips"; } -def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; -def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, - MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; + +let DecoderNamespace = "MicroMips" in { + def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; + def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32; +} + +let DecoderNamespace = "MicroMipsFP64" in { + def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64; + def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64; +} let DecoderNamespace = "MicroMips" in { def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, @@ -358,3 +399,12 @@ let AddedComplexity = 40 in { def : LoadRegImmPat<LWC1_MM, f32, load>, ISA_MICROMIPS; def : StoreRegImmPat<SWC1_MM, f32>, ISA_MICROMIPS; } + + def : MipsPat<(f32 (fpround FGR64Opnd:$src)), + (CVT_S_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS, FGR_64; + def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D64_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; + def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), + (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32; + def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td index aff8cca3020..0b2b1172ec4 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td @@ -730,7 +730,6 @@ class ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch { let Inst{9-8} = fmt; let Inst{7-0} = funct; - list<dag> Pattern = []; } class LWXC1_FM_MM<bits<9> funct> : MMArch { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index ba05b0f48df..427866d2bb0 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -108,6 +108,11 @@ static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { return true; } +void MipsTargetLowering::finalizeLowering(MachineFunction &MF) const { + MF.getFrameInfo().computeMaxCallFrameSize(MF); + TargetLoweringBase::finalizeLowering(MF); +} + // The MIPS MSA ABI passes vector arguments in the integer register set. // The number of integer registers used is dependant on the ABI used. MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index ce4f0376ca9..80dfada2924 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -370,6 +370,8 @@ class TargetRegisterClass; bool isJumpTableRelative() const override { return getTargetMachine().isPositionIndependent(); } + + void finalizeLowering(MachineFunction &MF) const override; protected: SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index ee69a202536..23fa4566106 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -364,7 +364,9 @@ def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; -defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; +let AdditionalPredicates = [NotInMicroMips] in { + defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; +} let AdditionalPredicates = [NotInMicroMips] in { def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, @@ -418,24 +420,26 @@ let AdditionalPredicates = [NotInMicroMips] in{ ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; } -def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, - ABSS_FM<0x20, 17>, FGR_32; +let AdditionalPredicates = [NotInMicroMips] in { + def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, + ABSS_FM<0x20, 17>, FGR_32; + def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABSS_FM<0x21, 16>, FGR_32; +} def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, ABSS_FM<0x21, 20>, FGR_32; -def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABSS_FM<0x21, 16>, FGR_32; let DecoderNamespace = "MipsFP64" in { - def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, - ABSS_FM<0x20, 17>, FGR_64; - let AdditionalPredicates = [NotInMicroMips] in{ + let AdditionalPredicates = [NotInMicroMips] in { def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 21>, FGR_64; + def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, + ABSS_FM<0x20, 17>, FGR_64; + def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, + ABSS_FM<0x21, 20>, FGR_64; + def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, + ABSS_FM<0x21, 16>, FGR_64; } - def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, - ABSS_FM<0x21, 20>, FGR_64; - def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, - ABSS_FM<0x21, 16>, FGR_64; def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x21, 21>, FGR_64; } @@ -456,7 +460,9 @@ let AdditionalPredicates = [NotInMicroMips] in { def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, ABSS_FM<0x7, 16>; -defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; +let AdditionalPredicates = [NotInMicroMips] in { + defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; +} let AdditionalPredicates = [NotInMicroMips] in { def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, @@ -508,15 +514,14 @@ let AdditionalPredicates = [NotInMicroMips] in { bitconvert>, MFC1_FM<5>, ISA_MIPS3; def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, bitconvert>, MFC1_FM<1>, ISA_MIPS3; -} - -def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, - ABSS_FM<0x6, 16>; -def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, FGR_32; -def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, FGR_64 { - let DecoderNamespace = "MipsFP64"; + def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, + ABSS_FM<0x6, 16>; + def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, + ABSS_FM<0x6, 17>, FGR_32; + def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, + ABSS_FM<0x6, 17>, FGR_64 { + let DecoderNamespace = "MipsFP64"; + } } /// Floating Point Memory Instructions @@ -586,18 +591,20 @@ let DecoderNamespace="MipsFP64" in { } /// Floating-point Aritmetic -def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, - ADDS_FM<0x00, 16>; -defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; -def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, - ADDS_FM<0x03, 16>; -defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; -def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, - ADDS_FM<0x02, 16>; -defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; -def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, - ADDS_FM<0x01, 16>; -defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; +let AdditionalPredicates = [NotInMicroMips] in { + def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, + ADDS_FM<0x00, 16>; + defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; + def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, + ADDS_FM<0x03, 16>; + defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; + def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, + ADDS_FM<0x02, 16>; + defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; + def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, + ADDS_FM<0x01, 16>; + defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; +} def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; @@ -861,10 +868,12 @@ def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), - (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), - (CVT_D32_S FGR32Opnd:$src)>, FGR_32; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), + (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; + def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D32_S FGR32Opnd:$src)>, FGR_32; +} def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; @@ -883,10 +892,12 @@ def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f32 (fpround FGR64Opnd:$src)), - (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), - (CVT_D64_S FGR32Opnd:$src)>, FGR_64; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(f32 (fpround FGR64Opnd:$src)), + (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; + def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), + (CVT_D64_S FGR32Opnd:$src)>, FGR_64; +} // To generate NMADD and NMSUB instructions when fneg node is present multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 0e0d82270c8..1f09ff1a6df 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -74,7 +74,9 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - return 28 - TFI->hasFP(MF); + bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed() + ? TFI->hasFP(MF) : true; + return 28 - HasFP; } case Mips::FGR32RegClassID: return 32; diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 59b7679971c..e9c08b9465a 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -379,28 +379,30 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); break; case Mips::PseudoCVT_D32_W: - expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); + Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; + expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); break; case Mips::PseudoCVT_S_L: expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); break; case Mips::PseudoCVT_D64_W: - expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); + Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; + expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); break; case Mips::PseudoCVT_D64_L: expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); break; case Mips::BuildPairF64: - expandBuildPairF64(MBB, MI, false); + expandBuildPairF64(MBB, MI, isMicroMips, false); break; case Mips::BuildPairF64_64: - expandBuildPairF64(MBB, MI, true); + expandBuildPairF64(MBB, MI, isMicroMips, true); break; case Mips::ExtractElementF64: - expandExtractElementF64(MBB, MI, false); + expandExtractElementF64(MBB, MI, isMicroMips, false); break; case Mips::ExtractElementF64_64: - expandExtractElementF64(MBB, MI, true); + expandExtractElementF64(MBB, MI, isMicroMips, true); break; case Mips::MIPSeh_return32: case Mips::MIPSeh_return64: @@ -651,6 +653,7 @@ void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + bool isMicroMips, bool FP64) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); @@ -682,7 +685,10 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, // We therefore pretend that it reads the bottom 32-bits to // artificially create a dependency and prevent the scheduler // changing the behaviour of the code. - BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) + BuildMI(MBB, I, dl, + get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) + : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), + DstReg) .addReg(SrcReg); } else BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); @@ -690,7 +696,7 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - bool FP64) const { + bool isMicroMips, bool FP64) const { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); @@ -735,7 +741,10 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, // We therefore pretend that it reads the bottom 32-bits to // artificially create a dependency and prevent the scheduler // changing the behaviour of the code. - BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) + BuildMI(MBB, I, dl, + get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) + : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), + DstReg) .addReg(DstReg) .addReg(HiReg); } else if (Subtarget.isABI_FPXX()) diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h index b356909bf1c..6ef8d3ccc4c 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h @@ -107,9 +107,11 @@ private: unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; void expandExtractElementF64(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, bool FP64) const; + MachineBasicBlock::iterator I, bool isMicroMips, + bool FP64) const; void expandBuildPairF64(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, bool FP64) const; + MachineBasicBlock::iterator I, bool isMicroMips, + bool FP64) const; void expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; }; diff --git a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll new file mode 100644 index 00000000000..33a86bbc5de --- /dev/null +++ b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 + +define double @add_d(double %a, double %b) { +; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32 +; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64 +; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM +; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM +; MMR6: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM + %1 = fadd double %a, %b + ret double %1 +} + +define double @sub_d(double %a, double %b) { +; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32 +; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64 +; MM: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32_MM +; MMFP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM +; MMR6: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM + %1 = fsub double %a, %b + ret double %1 +} + +define double @mul_d(double %a, double %b) { +; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32 +; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64 +; MM: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32_MM +; MMFP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM +; MMR6: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM + %1 = fmul double %a, %b + ret double %1 +} + +define double @div_d(double %a, double %b) { +; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32 +; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64 +; MM: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32_MM +; MMFP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM +; MMR6: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM + %1 = fdiv double %a, %b + ret double %1 +} + +define double @fneg(double %a) { +; MIPS32: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32 +; MIPS32FP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64 +; MM: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32_MM +; MMFP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM +; MMR6: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM + %1 = fsub double -0.000000e+00, %a + ret double %1 +} diff --git a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll new file mode 100644 index 00000000000..6593103de8d --- /dev/null +++ b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst \ +; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32R2 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \ +; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \ +; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \ +; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \ +; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMR6 + +define double @mthc1(i64 %a) { +; MIPS32R2: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32 +; MIPS32FP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64 +; MM: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32_MM +; MMFP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM +; MMR6: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM + %1 = bitcast i64 %a to double + ret double %1 +} + +define i64 @mfhc1(double %a) { +; MIPS32R2: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32 +; MIPS32FP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64 +; MM: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32_MM +; MMFP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM +; MMR6: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM + %1 = bitcast double %a to i64 + ret i64 %1 +} diff --git a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll new file mode 100644 index 00000000000..04368f202fa --- /dev/null +++ b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll @@ -0,0 +1,37 @@ +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 + +; TODO: Test for cvt_w_d is missing, could not generate instruction + +define double @cvt_d_s(float %a) { +; MIPS32: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S +; MIPS32FP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S +; MM: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S_MM +; MMFP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM +; MMR6: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM + %1 = fpext float %a to double + ret double %1 +} + +define double @cvt_d_w(i32 %a) { +; MIPS32: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W +; MIPS32FP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W +; MM: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W_MM +; MMFP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM +; MMR6: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM + %1 = sitofp i32 %a to double + ret double %1 +} + +define float @cvt_s_d(double %a) { +; MIPS32: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32 +; MIPS32FP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64 +; MM: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32_MM +; MMFP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM +; MMR6: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM + %1 = fptrunc double %a to float + ret float %1 +} diff --git a/llvm/test/CodeGen/Mips/maxcallframesize.ll b/llvm/test/CodeGen/Mips/maxcallframesize.ll new file mode 100644 index 00000000000..a980467eb29 --- /dev/null +++ b/llvm/test/CodeGen/Mips/maxcallframesize.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=mips-unknown-linux -stop-before=prologepilog | FileCheck %s + +; Test that maxCallFrameSize is being computed early on. + +@glob = external global i32* + +declare void @bar(i32*, [20000 x i8]* byval) + +define void @foo([20000 x i8]* %addr) { + %tmp = alloca [4 x i32], align 32 + %tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 + call void @bar(i32* %tmp0, [20000 x i8]* byval %addr) + ret void +} + +; CHECK: adjustsStack: true +; CHECK: maxCallFrameSize: 20008 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt index c9e8179f642..0d3836d0a03 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -208,3 +208,15 @@ 0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 +0x80 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f0 +0x80 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f0 +0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4 +0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4 +0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4 +0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 +0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 +0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 +0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 +0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 +0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt index 65525acee13..babbd3e082b 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt @@ -5,3 +5,15 @@ 0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 +0x80 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f0 +0x80 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f0 +0x82 0x54 0x30 0x01 # CHECK: add.d $f0, $f2, $f4 +0x82 0x54 0x70 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x82 0x54 0xb0 0x01 # CHECK: mul.d $f0, $f2, $f4 +0x82 0x54 0xf0 0x01 # CHECK: div.d $f0, $f2, $f4 +0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 +0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 +0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 +0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 +0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 +0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt index cd2265838c8..6a8866c1919 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt @@ -5,3 +5,15 @@ 0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 +0x54 0x80 0x38 0x3b # CHECK: mthc1 $4, $f0 +0x54 0x80 0x30 0x3b # CHECK: mfhc1 $4, $f0 +0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4 +0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4 +0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4 +0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4 +0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2 +0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2 +0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 +0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 +0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 +0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt index 560647bf2bf..14c1625f336 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -212,3 +212,15 @@ 0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 +0x54 0x80 0x38 0x3b # CHECK: mthc1 $4, $f0 +0x54 0x80 0x30 0x3b # CHECK: mfhc1 $4, $f0 +0x54 0x82 0x01 0x30 # CHECK: add.d $f0, $f2, $f4 +0x54 0x82 0x01 0x70 # CHECK: sub.d $f0, $f2, $f4 +0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4 +0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4 +0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2 +0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2 +0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 +0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 +0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 +0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt index 0e46c7245aa..c1b46f02d9a 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt @@ -5,3 +5,13 @@ 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 +0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4 +0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4 +0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 +0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 +0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 +0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 +0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 +0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 +0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 +0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt index 1c72fcabb09..08e7e54c4c0 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt @@ -5,3 +5,13 @@ 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 +0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4 +0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 +0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 +0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 +0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 +0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 +0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 +0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 +0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt index 80eaa5b11f9..d1abea5801b 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt @@ -5,3 +5,15 @@ 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 +0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4 +0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4 +0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 +0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 +0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 +0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 +0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 +0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 +0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 +0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 +0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt index 56de5c78b36..e784e526d63 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt @@ -5,3 +5,15 @@ 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 +0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4 +0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 +0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 +0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 +0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 +0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 +0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 +0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 +0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 +0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt index 15282ab50e0..d11e39f70ea 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt @@ -5,3 +5,15 @@ 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 +0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4 +0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4 +0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 +0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 +0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 +0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 +0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 +0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 +0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 +0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 +0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt index 5b9519ec23c..28404df6acf 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt @@ -5,3 +5,15 @@ 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 +0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4 +0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 +0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 +0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 +0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 +0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 +0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 +0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 +0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 +0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt index 478a7f2c4cc..f2e52f02caa 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt @@ -5,3 +5,15 @@ 0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 +0x00 0x10 0x24 0x46 # CHECK: add.d $f0, $f2, $f4 +0x01 0x10 0x24 0x46 # CHECK: sub.d $f0, $f2, $f4 +0x02 0x10 0x24 0x46 # CHECK: mul.d $f0, $f2, $f4 +0x03 0x10 0x24 0x46 # CHECK: div.d $f0, $f2, $f4 +0x06 0x10 0x20 0x46 # CHECK: mov.d $f0, $f2 +0x07 0x10 0x20 0x46 # CHECK: neg.d $f0, $f2 +0x24 0x10 0x20 0x46 # CHECK: cvt.w.d $f0, $f2 +0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 +0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 +0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 +0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt index 239dd4be7aa..1124b4dae87 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt @@ -5,3 +5,15 @@ 0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 +0x46 0x24 0x10 0x00 # CHECK: add.d $f0, $f2, $f4 +0x46 0x24 0x10 0x01 # CHECK: sub.d $f0, $f2, $f4 +0x46 0x24 0x10 0x02 # CHECK: mul.d $f0, $f2, $f4 +0x46 0x24 0x10 0x03 # CHECK: div.d $f0, $f2, $f4 +0x46 0x20 0x10 0x06 # CHECK: mov.d $f0, $f2 +0x46 0x20 0x10 0x07 # CHECK: neg.d $f0, $f2 +0x46 0x20 0x10 0x24 # CHECK: cvt.w.d $f0, $f2 +0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 +0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 +0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 +0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Mips/micromips/valid-fp64.s b/llvm/test/MC/Mips/micromips/valid-fp64.s index dbf758cfb4d..24bf1b8ca45 100644 --- a/llvm/test/MC/Mips/micromips/valid-fp64.s +++ b/llvm/test/MC/Mips/micromips/valid-fp64.s @@ -1,11 +1,35 @@ # RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \ # RUN: | FileCheck %s -abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM -abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM -sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM -sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM +abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x54,0x0c,0x23,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64_MM +abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM +add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM +cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM +cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM +cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM +cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM +div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM +mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM +mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM +mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM +mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64_MM +neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64_MM +sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64_MM +sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0x0a,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S_MM +sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64_MM diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index b30023f1660..d3c5d595a2a 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -58,6 +58,8 @@ sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x54,0x0c,0 sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x54,0x0c,0x4a,0x3b] # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D32_MM add $9, $6, $7 # CHECK: add $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x10] +add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D32_MM addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] addiu $9, $6, -15001 # CHECK: addiu $9, $6, -15001 # encoding: [0x31,0x26,0xc5,0x67] addi $9, $6, 17767 # CHECK: addi $9, $6, 17767 # encoding: [0x11,0x26,0x45,0x67] @@ -66,6 +68,8 @@ addu $9, $6, $7 # CHECK: addu $9, $6, $7 # encoding: [0x00,0x sub $9, $6, $7 # CHECK: sub $9, $6, $7 # encoding: [0x00,0xe6,0x49,0x90] subu $4, $3, $5 # CHECK: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0] sub $6, $zero, $7 # CHECK: neg $6, $7 # encoding: [0x00,0xe0,0x31,0x90] +sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x70] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D32_MM subu $6, $zero, $7 # CHECK: subu $6, $zero, $7 # encoding: [0x00,0xe0,0x31,0xd0] addu $7, $8, $zero # CHECK: addu $7, $8, $zero # encoding: [0x00,0x08,0x39,0x50] slt $3, $3, $5 # CHECK: slt $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x50] @@ -84,9 +88,13 @@ nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0x not $7, $8 # CHECK: not $7, $8 # encoding: [0x00,0x08,0x3a,0xd0] not $7 # CHECK: not $7, $7 # encoding: [0x00,0x07,0x3a,0xd0] mul $9, $6, $7 # CHECK: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10] +mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xb0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D32_MM mult $9, $7 # CHECK: mult $9, $7 # encoding: [0x00,0xe9,0x8b,0x3c] multu $9, $7 # CHECK: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c] div $zero, $9, $7 # CHECK: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c] +div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32_MM divu $zero, $9, $7 # CHECK: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c] sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00] sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] @@ -111,6 +119,8 @@ lwl $4, 16($5) # CHECK: lwl $4, 16($5) # encoding: [0x60,0x lwr $4, 16($5) # CHECK: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10] swl $4, 16($5) # CHECK: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10] swr $4, 16($5) # CHECK: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10] +mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x54,0x02,0x20,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D32_MM movz $9, $6, $7 # CHECK: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58] movn $9, $6, $7 # CHECK: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18] movt $9, $6, $fcc0 # CHECK: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b] @@ -121,10 +131,16 @@ mfhi $6 # CHECK: mfhi $6 # encoding: [0x46,0x # FIXME: MTLO should also have its 16 bit implementation selected in micromips mtlo $6 # CHECK: mtlo $6 # encoding: [0x00,0x06,0x3d,0x7c] mflo $6 # CHECK: mflo $6 # encoding: [0x46,0x46] +mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x54,0x80,0x30,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM +mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x54,0x80,0x38,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM madd $4, $5 # CHECK: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c] maddu $4, $5 # CHECK: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c] msub $4, $5 # CHECK: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c] msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c] +neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c] clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c] seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c] @@ -250,6 +266,14 @@ c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x5 c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x55,0x58,0xe1,0x7c] c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c] c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x54,0x9e,0x20,0x7c] +cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x54,0x02,0x49,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D32_MM +cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x54,0x02,0x13,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S_MM +cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x54,0x02,0x33,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W_MM +cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x54,0x02,0x1b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32_MM bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04] # CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08] diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 1a402983838..e64864f1d76 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -151,20 +151,26 @@ swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70] sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64_MM mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0] mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64_MM div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0] div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64_MM maddf.s $f3, $f4, $f5 # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8] maddf.d $f3, $f4, $f5 # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8] msubf.s $f3, $f4, $f5 # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8] msubf.d $f3, $f4, $f5 # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8] mov.s $f6, $f7 # CHECK: mov.s $f6, $f7 # encoding: [0x54,0xc7,0x00,0x7b] mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64_MM neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b] - neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b] + neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64_MM max.s $f5, $f4, $f3 # CHECK: max.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x0b] max.d $f5, $f4, $f3 # CHECK: max.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x0b] maxa.s $f5, $f4, $f3 # CHECK: maxa.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x2b] @@ -209,10 +215,14 @@ cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b] cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b] cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64_MM cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S_MM cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W_MM cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b] cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64_MM cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b] cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b] abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x54,0x0c,0x03,0x7b] @@ -319,6 +329,7 @@ mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64_MM mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc] mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc] @@ -327,6 +338,7 @@ mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4] mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64_MM mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c] tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] diff --git a/llvm/test/MC/Mips/mips1/valid.s b/llvm/test/MC/Mips/mips1/valid.s index bbd42e5ff2a..0de38beeaea 100644 --- a/llvm/test/MC/Mips/mips1/valid.s +++ b/llvm/test/MC/Mips/mips1/valid.s @@ -8,7 +8,8 @@ a: abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S add $s7,$s2,$a1 - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -32,14 +33,19 @@ a: c.sf.s $f14,$f22 cfc1 $s1,$21 ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -65,7 +71,8 @@ a: mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -73,7 +80,8 @@ a: mthi $s1 mtlo $sp mtlo $25 - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -83,7 +91,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nop nor $a3,$zero,$a3 @@ -121,7 +130,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 sw $ra,-10160($sp) diff --git a/llvm/test/MC/Mips/mips2/valid.s b/llvm/test/MC/Mips/mips2/valid.s index 97143f97396..3115375b41b 100644 --- a/llvm/test/MC/Mips/mips2/valid.s +++ b/llvm/test/MC/Mips/mips2/valid.s @@ -10,7 +10,8 @@ a: add $s7,$s2,$a1 add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -46,14 +47,19 @@ a: ceil.w.s $f6,$f20 cfc1 $s1,$21 ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -87,7 +93,8 @@ a: mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -95,7 +102,8 @@ a: mthi $s1 mtlo $sp mtlo $25 - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -105,7 +113,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nop nor $a3,$zero,$a3 @@ -155,7 +164,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 sw $ra,-10160($sp) diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s index 2582ba751ce..0bd87e83308 100644 --- a/llvm/test/MC/Mips/mips32/valid.s +++ b/llvm/test/MC/Mips/mips32/valid.s @@ -10,7 +10,8 @@ a: add $s7,$s2,$a1 add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -81,15 +82,20 @@ a: clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 deret div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -127,7 +133,8 @@ a: mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -151,7 +158,8 @@ a: mtlo $sp mtlo $25 mul $s0,$s4,$at - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -161,7 +169,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nop nor $a3,$zero,$a3 @@ -213,7 +222,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 sw $ra,-10160($sp) diff --git a/llvm/test/MC/Mips/mips32r2/valid-fp64.s b/llvm/test/MC/Mips/mips32r2/valid-fp64.s index bc06e418780..56b5ab85fab 100644 --- a/llvm/test/MC/Mips/mips32r2/valid-fp64.s +++ b/llvm/test/MC/Mips/mips32r2/valid-fp64.s @@ -1,11 +1,35 @@ # RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: FileCheck %s -abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S -abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 -sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S -sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 +abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S +add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64 +cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S +cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W +cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64 +cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64 +div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64 +mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64 +mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64 +mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64 +mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64 +neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64 +sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S +sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64 diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s index 2728897107a..27a26c72c47 100644 --- a/llvm/test/MC/Mips/mips32r2/valid.s +++ b/llvm/test/MC/Mips/mips32r2/valid.s @@ -10,7 +10,8 @@ a: add $s7,$s2,$a1 add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -81,19 +82,24 @@ a: clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W cvt.l.d $f24,$f15 cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 deret di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -138,11 +144,13 @@ a: maddu $24,$s2 mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 - mfhc1 $s8,$f24 + mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #1559 MFHC1_D32 mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -164,12 +172,14 @@ a: msubu $15,$a1 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 - mthc1 $zero,$f16 + mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #1712 MTHC1_D32 mthi $s1 mtlo $sp mtlo $25 mul $s0,$s4,$at - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -179,7 +189,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nmadd.d $f18,$f9,$f14,$f19 nmadd.s $f0,$f5,$f25,$f12 @@ -254,7 +265,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) diff --git a/llvm/test/MC/Mips/mips32r3/valid-fp64.s b/llvm/test/MC/Mips/mips32r3/valid-fp64.s index dc285f0ba0e..c228ff645d8 100644 --- a/llvm/test/MC/Mips/mips32r3/valid-fp64.s +++ b/llvm/test/MC/Mips/mips32r3/valid-fp64.s @@ -1,11 +1,35 @@ # RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: FileCheck %s -abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S -abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 -sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S -sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 +abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S +add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64 +cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S +cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W +cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64 +cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64 +div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64 +mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64 +mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64 +mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64 +mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64 +neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64 +sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S +sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64 diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s index ed9b3ee0527..87fc266d964 100644 --- a/llvm/test/MC/Mips/mips32r3/valid.s +++ b/llvm/test/MC/Mips/mips32r3/valid.s @@ -10,7 +10,8 @@ a: add $s7,$s2,$a1 add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -81,19 +82,24 @@ a: clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W cvt.l.d $f24,$f15 cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 deret di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -138,11 +144,13 @@ a: maddu $24,$s2 mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 - mfhc1 $s8,$f24 + mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #1559 MFHC1_D32 mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -164,12 +172,14 @@ a: msubu $15,$a1 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 - mthc1 $zero,$f16 + mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #1712 MTHC1_D32 mthi $s1 mtlo $sp mtlo $25 mul $s0,$s4,$at - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -179,7 +189,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nmadd.d $f18,$f9,$f14,$f19 nmadd.s $f0,$f5,$f25,$f12 @@ -254,7 +265,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) diff --git a/llvm/test/MC/Mips/mips32r5/valid-fp64.s b/llvm/test/MC/Mips/mips32r5/valid-fp64.s index f79a619ef78..a7d4a01ec10 100644 --- a/llvm/test/MC/Mips/mips32r5/valid-fp64.s +++ b/llvm/test/MC/Mips/mips32r5/valid-fp64.s @@ -1,11 +1,35 @@ # RUN: llvm-mc -arch=mips -mcpu=mips32r5 -mattr=+fp64 -show-encoding -show-inst %s | \ # RUN: FileCheck %s -abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S -abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 -sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S -sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] - # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D64 +abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S +add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64 +cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_S +cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D64_W +cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D64 +cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D64 +div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D64 +mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D64 +mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D64 +mthc1 $4, $f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D64 +mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D64 +neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D64 +sqrt.d $f0, $f12 # CHECK: sqrt.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_D64 +sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S +sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D64 diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s index ceb8c75e64d..5df06e8a914 100644 --- a/llvm/test/MC/Mips/mips32r5/valid.s +++ b/llvm/test/MC/Mips/mips32r5/valid.s @@ -10,7 +10,8 @@ a: add $s7,$s2,$a1 add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] - add.d $f1,$f7,$f29 + add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00] + # CHECK-NEXT: # <MCInst #1067 FADD_D32 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -81,19 +82,24 @@ a: clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 + cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21] + # CHECK-NEXT: # <MCInst #732 CVT_D32_S + cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21] + # CHECK-NEXT: # <MCInst #734 CVT_D32_W cvt.l.d $f24,$f15 cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 + cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20] + # CHECK-NEXT: # <MCInst #748 CVT_S_D32 cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 + cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24] + # CHECK-NEXT: # <MCInst #757 CVT_W_D32 cvt.w.s $f20,$f24 deret di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $zero,$25,$11 - div.d $f29,$f20,$f27 + div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03] + # CHECK-NEXT: # <MCInst #1105 FDIV_D32 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] @@ -139,11 +145,13 @@ a: maddu $24,$s2 mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc1 $a3,$f27 - mfhc1 $s8,$f24 + mfhc1 $4,$f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00] + # CHECK-NEXT: # <MCInst #1559 MFHC1_D32 mfhi $s3 mfhi $sp mflo $s1 - mov.d $f20,$f14 + mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06] + # CHECK-NEXT: # <MCInst #1160 FMOV_D32 mov.s $f2,$f27 move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25] move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25] @@ -165,12 +173,14 @@ a: msubu $15,$a1 mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01] mtc1 $s8,$f9 - mthc1 $zero,$f16 + mthc1 $4,$f0 # CHECK: mthc1 $4, $f0 # encoding: [0x44,0xe4,0x00,0x00] + # CHECK-NEXT: # <MCInst #1712 MTHC1_D32 mthi $s1 mtlo $sp mtlo $25 mul $s0,$s4,$at - mul.d $f20,$f20,$f16 + mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02] + # CHECK-NEXT: # <MCInst #1170 FMUL_D32 mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -180,7 +190,8 @@ a: neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22] negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] - neg.d $f27,$f18 + neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07] + # CHECK-NEXT: # <MCInst #1178 FNEG_D32 neg.s $f1,$f15 nmadd.d $f18,$f9,$f14,$f19 nmadd.s $f0,$f5,$f25,$f12 @@ -255,7 +266,8 @@ a: sub $s6,$s3,$12 sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] - sub.d $f18,$f3,$f17 + sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01] + # CHECK-NEXT: # <MCInst #1213 FSUB_D32 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) |
